Semiconductor memory system with bit line and method of manufacture thereof
View Patent ↗A semiconductor memory system and method of manufacture thereof including: a base wafer; an isolation region on the base wafer; an ion implanted region on the base wafer separated by the isolation region; a bit line contact plug over the ion implanted region; an isolation sidewall on the sides of the bit line contact plug; a resistor or capacitor on the isolation sidewall opposite the bit line contact plug between the bit line contact plug and another of the bit line contact plug; and a bit line over the resistor or capacitor and on the bit line contact plug.
1. A method of manufacture of a semiconductor memory system comprising:
forming isolation regions having contact holes on a base wafer including forming an ion implanted region in the contact holes;
depositing a bit line contact plug in one of the contact holes;
removing a portion of the isolation regions from between the bit line contact plug and another of the bit line contact plug including forming isolation sidewalls of the isolation regions in direct contact with sides of the bit line contact plug;
forming a resistor or capacitor on the isolation sidewalls opposite to the bit line contact plug between the bit line contact plug and another of the bit line contact plug; and
forming a bit line on the bit line contact plug and the another of the bit line contact plug and over the resistor or capacitor;
wherein forming the resistor or capacitor includes:
depositing a resistive or capacitive film on the isolation sidewalls between the bit line contact plug and the another of the bit line contact plug;
depositing a metal film on the resistive or capacitive film; and
planarizing a top surface of the isolation region, the bit line contact plug, the resistive or capacitive film, and the metal film.
2. The method as claimed in claim 1 wherein forming the bit line on the bit line contact plug includes forming a self-aligned bit line.
3. The method as claimed in claim 1 further comprising forming a node contact on the ion implanted region in the contact holes.
4. The method as claimed in claim 1 further comprising:
depositing a lower dielectric layer on the isolation regions and the resistor or capacitor; and
depositing an upper dielectric layer on the lower dielectric layer.
5. The method as claimed in claim 1 further comprising:
forming a node contact on the ion implanted region in the contact holes;
depositing a lower dielectric layer on the isolation regions and the resistor or capacitor; and
depositing an upper dielectric layer on the lower dielectric layer; and
wherein depositing a bit line contact plug in one of the contact holes includes:
depositing a bit line contact plug on the node contact in one of the contact holes over the ion implanted region.
6. The method as claimed in claim 5 further comprising:
patterning a photoresist on the upper dielectric layer;
removing the upper dielectric layer and the lower dielectric layer over the bit line contact plug; and
removing the photoresist.
7. The method as claimed in claim 5 wherein forming the bit line on the bit line contact plug includes patterning the lower dielectric layer and the upper dielectric layer for exposing the bit line contact plug.
8. The method as claimed in claim 5 wherein forming the isolation sidewalls includes exposing the node contact.
9. The method as claimed in claim 5 further comprising depositing an isolation layer over the lower dielectric layer.
10. A semiconductor memory system comprising:
a base wafer;
isolation regions on the base wafer;
an ion implanted region on the base wafer separated by the isolation regions;
a bit line contact plug over the ion implanted region;
isolation sidewalls on the sides of the bit line contact plug;
a resistor or capacitor on the isolation sidewalls opposite to the bit line contact plug between the bit line contact plug and another of the bit line contact plug, the resistor or capacitor including:
a resistive or capacitive film on the isolation sidewalls opposite to the bit line contact plug between the bit line contact plug and another of the bit line contact plug, and
a metal film on the resistive or capacitive film between the bit line contact plug and the another of the bit line contact plug; and
a bit line over the resistor or capacitor and on the bit line contact plug and the another of the bit line contact plug.
11. The system as claimed in claim 10 further comprising a node contact between and on the ion implanted region and the bit line contact plug.
12. The system as claimed in claim 10 wherein the bit line contact plug and the bit line form a self-aligned bit line.
13. The system as claimed in claim 10 wherein the resistor or capacitor on the isolation sidewalls opposite to the bit line contact plug is a self-aligned resistor or capacitor.
14. The system as claimed in claim 10 further comprising:
a node contact between and on the ion implanted region and the bit line contact plug;
a lower dielectric layer on the isolation regions, the metal film, and the resistive or capacitive film; and
an upper dielectric layer on the lower dielectric layer.
15. The system as claimed in claim 14 further comprising a protective conductive liner on the bit line contact plug and the bit line.
16. The system as claimed in claim 14 wherein the resistive or capacitive film and the metal film are protected from oxidation and etching damage by the lower dielectric layer and the upper dielectric layer.
17. The system as claimed in claim 14 wherein the resistive or capacitive film is a metal oxide or an electrolyte film for forming a resistor.
18. The system as claimed in claim 14 wherein the resistive or capacitive film is a high-k dielectric for forming a capacitor.