IP Library Granted Patent US 10,095,259
Granted Patent B1
US 10,095,259 · App. 13/789,908 · Granted Oct 9, 2018

Circuit arrangement for compensating current variations in current mirror circuit

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Quick Facts
Patent No.
US 10,095,259
App. No.
13/789,908
Granted
Oct 9, 2018
Kind
B1
Abstract

An electronic current mirror circuit particularly suitable for use in radio frequency (RF) and microwave power amplifiers. The electronic circuit includes a first current mirror circuit and a second current mirror circuit. The first current mirror circuit includes a first input circuit path and a first output circuit path, the first input circuit path is operated at a first supply voltage and the first output circuit path is operated at a second supply voltage. The second current mirror circuit includes a second input circuit path and a second output circuit path, the second input circuit path is operated at the second supply voltage, and the second output circuit path is connected to the first input circuit path so that variations in a current through the first output circuit path are compensated by a current in the second output circuit path.

Claims (28)

1. An electronic circuit comprising:

a first current mirror circuit having a first input circuit path and a first output circuit path, the first input circuit path being operated at a first supply voltage and the first output circuit path operated at a second supply voltage, the first input circuit path including a first input transistor having a collector terminal connected to a first voltage source through a first resistor and an emitter terminal grounded, the first output circuit path including a first output transistor having a collector terminal connected to a second voltage source through an inductive element, an emitter terminal grounded, and a base terminal connected to a base terminal of the first input transistor; and

a second current mirror circuit having a second input circuit path and a second output circuit path, the second input circuit path operated at the second supply voltage, and the second output circuit path connected to the first input circuit path so that variations in a current through the first output circuit path are compensated by a current in the second output circuit path, the second input circuit path including a second input transistor having a collector terminal connected to the second voltage source through a second resistor and an emitter terminal grounded, the second output circuit path including a second output transistor having a collector terminal connected to the collector terminal of the first input transistor, an emitter terminal grounded, and a base terminal connected to a base terminal of the second input transistor, the collector terminal of the second output transistor and the first resistor are connected to the first voltage source through a current control transistor, a drain terminal of the current control transistor is connected to the first voltage source, a gate terminal of the current control transistor is connected to the collector terminal of the first transistor, and a source terminal of the current control transistor is connected to the collector terminal of the first input transistor through the first resistor.

2. The electronic circuit as claimed in claim 1 wherein the current control transistor is a depletion mode field effect transistor.

3. The electronic circuit as claimed in claim 1 wherein the current control transistor is operated at a pinch off voltage associated with the current control transistor.

4. The electronic circuit as claimed in claim 1 wherein variations in the current through the first output transistor is compensated by the current through the second output transistor.

5. An electronic circuit comprising:

a first current mirror circuit having a first input circuit path and a first output circuit path, the first input circuit path being operated at a first supply voltage and the first output circuit path operated at a second supply voltage, the first input circuit path including a first input transistor having a collector terminal connected to a first voltage source through a first resistor and an emitter terminal grounded, the first output circuit path including a first output transistor having a collector terminal connected to a second voltage source through an inductive element, an emitter terminal grounded, and a base terminal connected to a base terminal of the first input transistor;

a second current mirror circuit having a second input circuit path and a second output circuit path, the second input circuit path operated at the second supply voltage, and the second output circuit path connected to the first input circuit path so that variations in a current through the first output circuit path are compensated by a current in the second output circuit path, the second input circuit path including a second input transistor having a collector terminal connected to the second voltage source through a second resistor and an emitter terminal grounded, the second output circuit path including a second output transistor having a collector terminal connected to the collector terminal of the first input transistor, an emitter terminal grounded, and a base terminal connected to a base terminal of the second input transistor; and

an error transistor, a base terminal of the error transistor connected to the first resistor, a collector terminal of the error transistor connected to the second voltage source, and a emitter terminal of the error transistor connected to the base terminal of the first output transistor and the first input transistor.

6. An electronic circuit comprising:

a first current mirror circuit including a first input transistor and a first output transistor, a collector terminal of the first input transistor connected to a first voltage source through a first resistor, a collector terminal of the first output transistor connected to a second voltage source, emitter terminals of the first input transistor and the first output transistor being grounded, and a base terminal of the first input transistor connected to a base terminal of the first output transistor; and

a second current mirror circuit including a second input transistor and a second output transistor, a collector terminal of the second input transistor connected to the second voltage source through a second resistor, a collector terminal of the second output transistor connected to the collector terminal of the first input transistor, emitter terminals of the second input transistor and the second output transistor being grounded, and a base terminal of the second input transistor connected to a base terminal of the second output transistor, the collector terminal of the second output transistor and the first resistor connected to the first voltage source through a current control transistor, a drain terminal of the current control transistor connected to the first voltage source, a gate terminal of the current control transistor connected to the collector terminal of the first transistor and a source terminal of the current control transistor connected to the collector terminal of the first input transistor through the first resistor.

7. The electronic circuit as claimed in claim 6 wherein the current control transistor is operated at a predetermined pinch off voltage associated with the current control transistor.

8. The electronic circuit as claimed in claim 6 wherein variations in a current through the first output transistor is compensated by a current through the second output transistor.

9. The electronic circuit as claimed in claim 6 wherein the collector terminal of the first output transistor is connected to the second voltage source through an inductive element.

10. The electronic circuit as claimed in claim 6 wherein the collector terminal and the base terminal of the first input transistor are connected together, and the collector terminal and the base terminal of the second input transistor are connected together.

11. An electronic circuit comprising:

a first current mirror circuit including a first input transistor and a first output transistor, a collector terminal of the first input transistor connected to a first voltage source through a first resistor, a collector terminal of the first output transistor connected to a second voltage source, emitter terminals of the first input transistor and the first output transistor being grounded, and a base terminal of the first input transistor connected to a base terminal of the first output transistor;

a second current mirror circuit including a second input transistor and a second output transistor, a collector terminal of the second input transistor connected to the second voltage source through a second resistor, a collector terminal of the second output transistor connected to the collector terminal of the first input transistor, emitter terminals of the second input transistor and the second output transistor being grounded, and a base terminal of the second input transistor connected to a base terminal of the second output transistor, and

an error transistor, a base terminal of the error transistor connected to the first resistor, a collector terminal of the error transistor connected to the second voltage source, and a emitter terminal of the error transistor connected to the base terminal of the first output transistor and the first input transistor.

12. An electronic circuit comprising:

a first current mirror circuit including a current control transistor, a first input transistor, a first output transistor, and an error transistor, a drain terminal of the current control transistor connected to a first voltage source, a source terminal of the current control transistor connected to a collector terminal of the first input transistor through a first resistor, a gate terminal of the current control transistor connected to the collector terminal of the first input transistor, emitter terminals of the first input transistor and the first output transistor being grounded, a base terminal of the error transistor connected to the source terminal of the current control transistor, a collector terminal of the error transistor connected to a second voltage source, and an emitter terminal of the error transistor, the base terminals of the first input transistor, and the first output transistor being connected, a collector terminal of the first output transistor connected to the second voltage source through an inductive element; and

a second current mirror circuit including a second input transistor and a second output transistor, a collector terminal of the second input transistor connected to the second voltage source through a first resistor, a collector terminal of the second output transistor connected to the source terminal of the current control transistor, emitter terminals of the second input transistor and the second output transistor being grounded, and a base terminal of the second input transistor connected to a base terminal of the second output transistor.

13. The electronic circuit as claimed in claim 12 wherein each of the first input transistor, the first output transistor, the second input transistor, the second output transistor, and the error transistor is a hetero-junction bipolar transistor.

14. The electronic circuit as claimed in claim 12 wherein the negative voltage feedback due to the first resistor results in a stabilized collector current of the first input transistor.

15. The electronic circuit as claimed in claim 12 wherein the collector current of the second output transistor compensates for a variation in the collector current of the first output transistor.

16. The electronic circuit as claimed in claim 12 wherein variations in the collector current of the first output transistor caused by temperature variations is compensated by the collector current of the second output transistor.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 24, 2017
From: II-VI OPTOELECTRONIC DEVICES, INC.
To: SKYWORKS SOLUTIONS, INC.
Reel/Frame 042551/0708 →
CHANGE OF NAME Recorded May 1, 2017
From: ANADIGICS, INC.
To: II-VI OPTOELECTRONIC DEVICES, INC.
Reel/Frame 042381/0761 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUS NUMBER 6790900 AND REPLACE IT WITH 6760900 PREVIOUSLY RECORDED ON REEL 034056 FRAME 0641. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT. Recorded Nov 21, 2016
From: ANADIGICS, INC.
To: SILICON VALLEY BANK
Reel/Frame 040660/0967 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 037973 FRAME: 0226. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT. Recorded May 18, 2016
From: ANADIGICS, INC.
To: II-VI INCORPORATED
Reel/Frame 038744/0835 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2016
From: II-VI INCORPORATED
To: ANADIGICS, INC.
Reel/Frame 038119/0312 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Mar 1, 2016
From: ANADIGICS, INC.
To: II-IV INCORPORATED
Reel/Frame 037973/0226 →
RELEASE OF SECURITY INTEREST Recorded Mar 1, 2016
From: SILICON VALLEY BANK
To: ANADIGICS, INC.
Reel/Frame 037973/0133 →
SECURITY AGREEMENT Recorded Oct 27, 2014
From: ANADIGICS, INC.
To: SILICON VALLEY BANK
Reel/Frame 034056/0641 →