Pipelining in a memory
View Patent ↗A system including a memory cell array including a plurality of memory cells, and a writing device to generate multiple back-to-back write pulses to write to target memory cells from among the plurality of memory cells, the multiple back-to-back write pulses overlapping during an overlap duration, the overlap duration being adjustable based on a performance parameter of the memory cell array.
1. A system comprising:
a memory cell array including a plurality of memory cells; and
a writing device configured to generate multiple back-to-back write pulses configured to write to target memory cells from among the plurality of memory cells, the multiple back-to-back write pulses overlapping during an overlap duration, the overlap duration being configured to be adjusted based on a performance parameter of the memory cell array,
wherein, during the overlap duration, a ramp-up period of a bitine associated with writing to a subsequent target memory cell substantially overlaps a steady-state period of a bitline associated with writing to a current target memory cell.
2. The system of claim 1 , wherein the performance parameter comprises a current required to pre-charge and to program a target memory cell.
3. The system of claim 1 , wherein the performance parameter comprises a current required to pre-charge and to erase a target memory cell.
4. The system of claim 1 , wherein the performance parameter comprises a predetermined current consumption by a memory comprised of the memory cell array.
5. The system of claim 1 , wherein the ramp-up period of the bitline associated with writing to the subsequent target memory cell includes a plurality of ramp-up stages, the plurality of ramp-up stages being driven by respective ramp-up voltages.
6. The system of claim 1 , comprising:
a ramp control circuit configured to:
receive a plurality of ramp-up voltages; and
drive, during the ramp-up period, a plurality of ramp-up stages of the bitline associated with writing to the subsequent target memory cell by applying a respective one of a plurality of ramp-up voltages.
7. The system of claim 6 , wherein the ramp control circuit is configured to sequentially apply the plurality of ramp-up voltages to drive the plurality of ramp-up stages.
8. The system of claim 6 , wherein the ramp control circuit is configured to receive the plurality of ramp-up voltages from respective independent voltage supplies, each independent voltage supply having a respective regulator.
9. The system of claim 6 , wherein the ramp control circuit is configured to receive the plurality of ramp-up voltages from a single voltage supply generating the plurality of ramp-up voltages, each ramp-up voltage being regulated independently.
10. A method in a system for writing to memory cells, the method comprising:
generating back-to-back first and subsequent write pulses to enable writing to target memory cells, the first and subsequent programming pulses overlapping during an overlap duration that is adjustable based on a performance parameter of the system; and
writing to the target memory cells using the first and subsequent write pulses,
wherein the writing includes substantially overlapping, during the overlap duration, an ramp-up period of a bitline associated with writing to a subsequent target memory cell with a steady-state period of a bitline associated with writing to a current target memory cell.
11. The method of claim 10 , wherein the performance parameter comprises a current required to precharge and program a target memory cell.
12. The method of claim 10 , wherein the performance parameter comprises a current required to precharge and to erase a target memory cell.
13. The method of claim 10 , wherein the performance parameter comprises a predetermined current consumption by a memory comprised of the memory cell array.
14. The method of claim 10 , wherein the ramp-up period of the bitline associated with writing to the subsequent target memory cell includes a plurality of ramp-up stages, the plurality of ramp-up stages being driven by respective ramp-up voltages.
15. The method of claim 10 , comprising:
receiving a plurality of ramp-up voltages; and
driving, during the ramp-up period, a plurality of ramp-up stages of the bitline associated with writing to the subsequent target memory cell by applying a respective one of the plurality of ramp-up voltages.
16. The method of claim 15 , wherein the applying comprises sequentially applying the respective one of the plurality of ramp-up voltages to drive the plurality of ramp-up stages.
17. The method of claim 15 , wherein the receiving a plurality of ramp-up voltages includes receiving the plurality of ramp-up voltages from corresponding respective voltage supplies.
18. The method of claim 15 , wherein the receiving a plurality of ramp-up voltages includes receiving the plurality of ramp-up voltages from a single voltage supply generating the plurality of ramp-up voltages, each ramp-up voltage being regulated independently.