Semiconductor device and method for manufacturing the same

1. A method for manufacturing a semiconductor device comprising:

forming a lower electrode pattern on a substrate;

forming a first insulating layer on the lower electrode pattern;

forming an upper electrode pattern on the first insulating layer;

forming an etch blocking spacer at a side of the upper electrode pattern;

forming a second insulating layer on the upper electrode pattern;

etching the second insulating layer to form a cavity which exposes the etch blocking spacer; and

forming a contact ball in the cavity.

2. The method as claimed in claim 1 , further comprising forming an etch stop film on the lower electrode pattern before forming the first insulating layer.

3. The method as claimed in claim 1 , wherein forming the lower electrode pattern includes forming a plurality of lower electrodes spaced apart from one another on the substrate.

4. The method as claimed in claim 1 , wherein forming the upper electrode pattern includes forming a plurality of the upper electrodes spaced apart from one another on the first insulating layer.

5. The method as claimed in claim 4 , wherein forming the etch blocking spacer includes forming an etch blocking spacer to cover a side of each of the plurality of upper electrodes.

6. The method as claimed in claim 5 , wherein forming the etch blocking spacer further includes:

forming a conductive material layer on an uppermost surface and at a side of each of the plurality of upper electrodes, and on an uppermost surface of the first insulating layer, and

etching back the conductive material layer to form the etch blocking spacer.

7. The method as claimed in claim 5 , wherein forming the etch blocking spacer further includes:

forming an insulating material layer on the uppermost surface and at the side of each of the plurality of upper electrodes and on the uppermost surface of the first insulating layer,

forming a conductive material layer on the insulating material layer, and

etching back the conductive material layer and the insulating material layer to form the etch blocking spacer.

8. The method as claimed in claim 5 , wherein forming the etch blocking spacer further includes:

forming an insulating material layer on the uppermost surface and at the side of each of the plurality of upper electrodes and on the uppermost surface of the first insulating layer,

etching back the insulating material layer to form a first spacer,

forming a conductive material layer on the uppermost surface and at an upper side surface of each of the plurality of upper electrodes, on the first spacer, and on the uppermost surface of the first insulating layer, and

etching back the conductive material layer to form the etch blocking spacer.

9. The method as claimed in claim 1 , wherein etching the second insulating layer to form the cavity includes:

etching the second insulating layer and the first insulating layer to form a hole therein which exposes the etch stop film; and

further etching the second insulating layer and the first insulating layer to form the cavity which exposes the etch blocking spacer.

10. The method as claimed in claim 2 , further comprising forming a contact in contact with the lower electrode pattern passing through the first insulating layer and the etch stop film, wherein the second upper electrode pattern is in contact with the contact.

11. The method as claimed in claim 2 , wherein the upper electrode pattern comprises a material selected from Al, Cu, Au, and alloys including at least one of Al, Cu, and Au,

the etch stop film comprises a silicon nitride film, and

the first insulating layer and the second insulating layer include at least one of SiO 2 , Si x N y (where x and y are real numbers >0), fluorosilicate glass, undoped silicate glass, borophosphosilicate glass, and tetraethoxysilane, and the etch blocking layer comprises tungsten.

12. The method as claimed in claim 6 , wherein the conductive material layer includes at least one of TiN, Ti, W, Au, Ag, and doped Si.

13. The method as claimed in claim 7 , wherein the insulating material layer includes at least one of SiO 2 , SiN, Si, HfO 2 , Al 2 O 3 , and SiON, and the conductive material layer includes at least one of TiN, Ti, W, Au, Ag, and doped Si.