IP Library Granted Patent US 9,240,775
Granted Patent B2
US 9,240,775 · App. 13/795,506 · Granted Jan 19, 2016

Circuit arrangements

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Quick Facts
Patent No.
US 9,240,775
App. No.
13/795,506
Granted
Jan 19, 2016
Kind
B2
Abstract

A circuit arrangement may include: a first bipolar transistor; a second bipolar transistor; wherein the circuit arrangement is configured to provide a first current flowing through the first bipolar transistor and a second current flowing through the second bipolar transistor; a resistor connected between a first input of the first bipolar transistor and a first input of the second bipolar transistor; a first circuit configured to provide a first current flowing through the resistor to a first input node of the first bipolar transistor, and a second circuit configured to provide a reference current to the first input node of the first bipolar transistor, wherein the first current and the reference current have different temperature dependencies.

Claims (22)

1. A circuit arrangement, comprising:

a first bipolar transistor;

a second bipolar transistor;

wherein the circuit arrangement is configured to provide a first current flowing through the first bipolar transistor and a second current flowing through the second bipolar transistor;

a resistor electrically coupled between a first input of the first bipolar transistor and a first input of the second bipolar transistor;

a first circuit configured to provide a first current flowing through the resistor to a first input node of the first bipolar transistor,

a second circuit configured to provide a reference current to the first input node of the first bipolar transistor, wherein the first current and the reference current comprise different temperature dependencies.

2. The circuit arrangement of claim 1 ,

wherein the first and the second bipolar transistor are npn transistors.

3. The circuit arrangement of claim 1 ,

wherein the emitters of the first and the second bipolar transistor are electrically coupled to a common node.

4. The circuit arrangement of claim 1 , further comprising:

a first current mirror circuit configured to provide the first collector current and the second collector current at a constant ratio between said collector currents.

5. The circuit arrangement of claim 1 , further comprising:

an inner control loop controlling the first current through the resistor depending on the collector current of the first bipolar transistor or controlling the first current through the resistor depending on the collector current of the second bipolar transistor.

6. The circuit arrangement of claim 1 , further comprising:

a current comparator configured to provide a current difference signal depending on a difference between the first current flowing through the resistor and the reference current.

7. The circuit arrangement of claim 6 , further comprising:

a control circuit configured to control the second circuit, wherein the second circuit is configured to provide the reference current depending on the current difference signal.

8. The circuit arrangement of claim 1 , further comprising:

a third circuit configured to provide a third current to the base node of the first bipolar transistor.

9. The circuit arrangement of claim 8 , wherein the third circuit configured to provide the third current comprises a non-linear element.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2022
From: INTEL DEUTSCHLAND GMBH
To: INTEL CORPORATION
Reel/Frame 061356/0001 →
CHANGE OF NAME Recorded Nov 6, 2015
From: INTEL MOBILE COMMUNICATIONS GMBH
To: INTEL DEUTSCHLAND GMBH
Reel/Frame 037057/0061 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2013
From: EBERLEIN, MATTHIAS
To: INTEL MOBILE COMMUNICATIONS GMBH
Reel/Frame 030211/0670 →