Variable resistance memory device with shunt gate connected to corresponding gate

1. A variable resistance memory device, comprising:

a semiconductor substrate having a length and a width;

a plurality of vertical transistors, extending from a surface of the semiconductor substrate in a direction perpendicular to the length and the width of the semiconductor substrate, the plurality of vertical transistors being arranged at a fixed interval on the semiconductor substrate;

a variable resistive region formed on each of the plurality of vertical transistors; and

a shunt gate disposed in a space between adjacent vertical transistors and configured to be electrically connected to a gate of each of the plurality of vertical transistors.

2. The variable resistance memory device of claim 1 , wherein each of the plurality of vertical transistors includes:

a pillar extending from the surface of the semiconductor substrate in the direction perpendicular to the length and the width of the semiconductor substrate; and

a surround gate to surround a lower region of the pillar.

3. The variable resistance memory device of claim 2 , wherein the shunt gate is to connect to an adjacent surround gate.

4. The variable resistance memory device of claim 1 , wherein the shunt gate extends from the surface of the semiconductor substrate in the direction perpendicular to the length and the width of the semiconductor substrate, the shunt gate including:

a first portion to contact the adjacent surround gate, and

a second portion, connected to the first portion, wherein the second portion is wider than the first portion in a direction parallel to the surface of the semiconductor substrate.

5. The variable resistance memory device of claim 4 , wherein the second portion extends in a space between the variable resistive regions.

6. The variable resistance memory device of claim 4 , wherein an insulating spacer is interposed between the first portion and the pillar.