Semiconductor device

1. A semiconductor device comprising:

a semiconductor body including

a first upper surface,

a first side surface extending downwardly from the first upper surface,

a second upper surface,

a second side surface extending downwardly from the second upper surface, and

a bottom surface interfacing the first and second side surfaces with each other,

the first and second side surfaces and the bottom surface cooperating with one another to define a groove;

a conductive film partially filling the groove with an intervention of an insulating film therebetween such that the conductive film terminates at a first intermediate portion of the first side surface between the first upper surface and the bottom surface and at a second intermediate portion of the second side surface between the second upper surface and the bottom surface,

a first distance between the first intermediate portion of the first side surface and the first upper surface being greater than a second distance between the second intermediate portion of the second side surface and the second upper surface,

the insulating film covering a portion of inner surfaces of the groove, said portion of inner surfaces of the groove corresponding to a gate electrode formation area, and

the conductive film being a base material of a gate electrode formed in the gate electrode formation area;

a first impurity diffusion region adjacent the first upper surface;

a second impurity diffusion region adjacent the second upper surface; and

an interlayer dielectric film over the gate electrode in the groove,

wherein the gate electrode includes a first gate electrode upper surface, a second gate electrode upper surface, and a step between the first gate electrode upper surface and the second gate electrode upper surface,

wherein the second impurity diffusion region does not overlap with the gate electrode, and

wherein a top surface of at least a portion of the interlayer dielectric film is lower than a top surface of the first impurity diffusion region.

2. The device as claimed in claim 1 , wherein the first and second upper surfaces are substantially coplanar with each other.

3. The device as claimed in claim 2 , wherein the conductive film includes an uneven top surface to terminate at the first and second intermediate portions of the first and second side surfaces, respectively.

4. The device as claimed in claim 3 , wherein the conductive film includes a stepwise top surface to terminate at the first and second intermediate portions of the first and second side surfaces, respectively.

5. The device as claimed in claim 1 , further comprising:

a first conductor formed so as to be held in contact with the first upper surface and be electrically connected to the first impurity diffusion region; and

a second conductor formed so as to be held in contact with the second upper surface and be electrically connected to the second impurity diffusion region.

6. The device as claimed in claim 5 , further comprising:

a plurality of field effect transistors each including the groove;

a capacitor electrically connected to the first conductor and allocated to each of the plurality of field effect transistors; and

a conductive wire electrically connected to the second conductor and shared among the plurality of field effect transistors.

7. The device as claimed in claim 1 , wherein the interlayer dielectric film includes another portion having a top surface higher than the top surface of the first impurity diffusion region.

8. The device as claimed in claim 1 , further comprising a bit contact plug over the interlayer dielectric film, the bit contact plug being in contact with the top surface and a side surface of the first impurity diffusion region.

9. A semiconductor device comprising:

a semiconductor body including

a first upper surface having a first edge,

a first side surface extending downwardly from the first upper surface,

a second upper surface having second and third edges,

a second side surface extending downwardly from the second edge of the second upper surface,

a first bottom surface interfacing the first and second side surfaces with each other,

a third side surface extending downwardly from the third edge of the second upper surface,

a third upper surface having a fourth edge,

a fourth side surface extending downwardly from the fourth edge of the third upper surface, and

a second bottom surface interfacing the third and fourth side surfaces with each other,

the first and second side surfaces and the first bottom surface cooperating with one another to define a first groove, the third and fourth side surfaces and the second bottom surface cooperating with one another to define a second groove;

a first conductive film partially filling the first groove with an intervention of a first insulating film therebetween such that the first conductive film terminates at a first intermediate portion of the first side surface between the first edge of the first upper surface and the first bottom surface and at a second intermediate portion of the second side surface between the second edge of the second upper surface and the first bottom surface,

a first distance between the first intermediate portion of the first side surface and the first edge of the first upper surface being greater than a second distance between the second intermediate portion of the second side surface and the second edge of the second upper surface,

the first insulating film covering a portion of inner surfaces of the first groove, said portion of inner surfaces of the first groove corresponding to a first gate electrode formation area, and

the first conductive film being a base material of a first gate electrode formed in the first gate electrode formation area;

a second conductive film partially filling the second groove with an intervention of a second insulating film therebetween such that the second conductive film terminates at a third intermediate portion of the third side surface between the third edge of the second upper surface and the second bottom surface and at a fourth intermediate portion of the fourth side surface between the fourth edge of the third upper surface and the second bottom surface, a third distance between the third intermediate portion of the third side surface and the third edge of the second upper surface being shorter than a fourth distance between the fourth intermediate portion of the fourth side surface and the fourth edge of the third upper surface,

a first impurity diffusion region adjacent the first upper surface;

a second impurity diffusion region adjacent the second upper surface;

a third impurity diffusion region adjacent the third upper surface; and

a first interlayer dielectric film over the first gate electrode in the first groove,

wherein the first gate electrode includes a first gate electrode upper surface, a second gate electrode upper surface, and a step between the first gate electrode upper surface and the second gate electrode upper surface,

wherein the second impurity diffusion region does not overlap with the first gate electrode, and

wherein a top surface of at least a portion of the first interlayer dielectric film is lower than a top surface of the first impurity diffusion region.

10. The device as claimed in claim 9 , wherein the first, second and third upper surfaces are substantially coplanar with each other.

11. The device as claimed in claim 10 ,

wherein the first conductive film includes a first uneven top surface to terminate at the first and second intermediate portions of the first and second side surfaces, respectively, and

the second conductive film includes a second uneven top surface to terminate at the third and fourth intermediate portions of the third and fourth side surfaces, respectively.

12. The device as claimed in claim 11 ,

wherein the first conductive film includes a first stepwise top surface to terminate at the first and second intermediate portions of the first and second side surfaces, respectively, and

the second conductive film includes a second stepwise top surface to terminate at the third and fourth intermediate portions of the third and fourth side surfaces, respectively.

13. The device as claimed in claim 9 , further comprising:

a first conductor formed so as to be held in contact with the first upper surface and be electrically connected to the first impurity diffusion region;

a second conductor formed so as to be held in contact with the second upper surface and be electrically connected to the second impurity diffusion region; and

a third conductor formed so as to be held in contact with the third upper surface and be electrically connected to the third impurity diffusion region.

14. The device as claimed in claim 13 , further comprising:

a plurality of field effect transistors each including the first or second groove;

a capacitor electrically connected to the first or third conductor and allocated to each of the plurality of field effect transistors; and

a conductive wire electrically connected to the second conductor and shared among the plurality of field effect transistors.

15. The device as claimed in claim 9 , wherein the first interlayer dielectric film includes another portion having a top surface higher than the top surface of the first impurity diffusion region.

16. The device as claimed in claim 9 , further comprising a first bit contact plug over the first interlayer dielectric film, the first bit contact plug being in contact with the top surface and a side surface of the first impurity diffusion region.