Semiconductor device and structure

1. A 3D device, comprising:

a first layer comprising first transistors, said first transistors interconnected by a first layer of interconnection;

a second layer comprising second transistors, said second transistors overlaying said first layer of interconnection;

wherein said first layer comprises a first clock distribution structure, said first clock distribution structure comprising a first clock origin,

wherein said second layer comprises a second clock distribution structure, said second clock distribution structure comprises a second clock origin, and

wherein said second clock origin is feeding said first clock origin.

2. A 3D device according to claim 1 ,

wherein said second clock distribution structure comprises a clock tree.

3. A 3D device according to claim 1 ,

wherein said second clock distribution structure comprises a clock mesh.

4. A 3D device according to claim 1 ,

wherein said second clock distribution structure comprises at least one cross-link to connect it to said first clock distribution structure.

5. A mobile system comprising a 3D device according to claim 1 .

6. A 3D device according to claim 1 , further comprising:

an electronic circuit comprised by said second transistors;

wherein said first layer comprises a plurality of first flip-flops connected to form a first scan chain, and

wherein said first scan chain is connected to provide scan information to said electronic circuit.

7. A 3D device according to claim 1 ,

wherein said first layer comprises a first bus, said first bus interconnecting a plurality of first logic units,

wherein said second layer comprises a second bus, said second bus interconnecting a plurality of second logic units, and

wherein said first bus and said second bus are interconnected so said second logic units could communicate through said first bus with at least one of said first logic units.

8. A mobile system comprising a 3D device according to claim 1 .

9. A 3D device, comprising:

a first layer comprising first transistors said first transistors interconnected by a first layer of interconnection;

a second layer comprising second transistors, said second transistors overlaying said first layer of interconnection;

an electronic circuit comprised by said second transistors;

wherein said first layer comprises a plurality of first flip-flops connected to form a first scan chain, and

wherein said first scan chain is connected to provide scan information to said electronic circuit.

10. A 3D device according to claim 9 ,

wherein said second layer is connected to said first layer to provide test information to said first scan chain.

11. A 3D device according to claim 9 , further comprising:

a wireless communication circuit,

wherein said wireless communication circuit enables wireless testing of said device while said device is still is part of a wafer.

12. A 3D device according to claim 9 ,

wherein said device is designed to be tested in wafer form before said second layer has been overlaid.

13. A mobile system comprising a 3D device according to claim 9 .

14. A 3D device according to claim 9 ,

wherein said first layer comprises a first clock distribution structure, said first clock distribution structure comprising a first clock origin,

wherein said second layer comprises a second clock distribution structure, said second clock distribution structure comprising a second clock origin, and

wherein said second clock origin is feeding said second clock origin.

15. A 3D device according to claim 9 ,

wherein said first layer comprises a first bus, said first bus interconnecting a plurality of first logic units,

wherein said second layer comprises a second bus, said second bus interconnecting a plurality of second logic units, and

wherein said first bus and said second bus are interconnected so said second logic units could communicate through said first bus with at least one of said first logic units.

16. A 3D device, comprising:

a first layer comprising first transistors, said first transistors interconnected by a first layer of interconnection;

a second layer comprising second transistors, said second transistors overlaying said first layer of interconnection;

wherein said first layer comprises a first bus, said first bus interconnecting a plurality of first logic units,

wherein said second layer comprises a second bus, said second bus interconnecting a plurality of second logic units, and

wherein said first bus and said second bus are interconnected so said second logic units could communicate through said first bus with at least one of said first logic units.

17. A 3D device according to claim 16 ,

wherein at least one of said second logic units has a plurality of connections to an external component.

18. A 3D device according to claim 16 , wherein said first bus is one of the following:

i.) an Advanced Microcontroller Bus Architecture (AMBA) bus;

ii) a CoreConnect bus;

iii) a STBus;

iv.) a Wishbone bus;

v.) an Open Core Protocol (OCP) bus, or

vi.) a Virtual Component Interface (VCI) bus.

19. A 3D device according to claim 16 ,

wherein said first layer comprises a first clock distribution structure, said first clock distribution structure comprises a first clock origin,

wherein said second layer comprises a second clock distribution structure, said second clock distribution structure comprises a second clock origin, and

wherein said second clock origin is feeding said first clock origin.

20. A 3D device according to claim 16 , further comprising:

an electronic circuit comprised by said second transistors;

wherein said first layer comprises a plurality of first flip-flops connected to form a first scan chain, and

wherein said first scan chain is connected to provide scan information to said electronic circuit.