Semiconductor package
View Patent ↗A semiconductor package includes a first substrate, a plurality of memory chips horizontally disposed on the first substrate, and having one surfaces which face the first substrate, other surfaces which face away from the one surfaces, and first bumps formed on the other surfaces, a second substrate disposed on the plurality of memory chips and electrically connected, a sub-substrate horizontally disposed on the first substrate together with the plurality of memory chips and electrically connecting the first substrate and the second substrate, and a driving chip having second bumps on one surface thereof and mounted to the second substrate such that the second bumps are electrically connected with the second substrate.
1. A semiconductor package comprising:
a first substrate;
a plurality of memory chips horizontally disposed on the first substrate, and having one surfaces which face the first substrate, other surfaces which face away from the one surfaces, and first bumps formed on the other surfaces;
a second substrate disposed on the plurality of memory chips and electrically connected with the first bumps;
a sub-substrate horizontally disposed on the first substrate together with the plurality of memory chips and electrically connecting the first substrate and the second substrate; and
a driving chip having second bumps on one surface thereof and mounted to the second substrate such that the second bumps are electrically connected with the second substrate.
2. The semiconductor package according to claim 1 , wherein the plurality of memory chips are constituted by the same kind of memory chips which have a substantially similar structures.
3. The semiconductor package according to claim 1 , wherein the plurality of memory chips are constituted by at least two kinds of memory chips which have different structures.
4. The semiconductor package according to claim 3 , wherein the plurality of memory chips features a center pad type structure.
5. The semiconductor package according to claim 3 , wherein the plurality of memory chips features an edge pad type structure.
6. The semiconductor package according to claim 1 , wherein the plurality of memory chips are disposed in a matrix manner when viewed in plan view.
7. The semiconductor package according to claim 6 , wherein the plurality of memory chips have major axes aligned parallel to each other.
8. The semiconductor package according to claim 7 , wherein the sub-substrate is disposed in a direction of the major axes of the memory chips when viewed in plan view.
9. The semiconductor package according to claim 7 , wherein the sub-substrate is disposed in a direction of minor axes of the memory chips when viewed in plan view.
10. The semiconductor package according to claim 1 , wherein the plurality of memory chips and the sub-substrate are disposed in a matrix manner when viewed in plan view.
11. The semiconductor package according to claim 1 , further comprising:
adhesive members attaching the first substrate and the plurality of memory chip to each other.
12. The semiconductor package according to claim 1 , further comprising:
a molding part sealing an upper surface of the first substrate and encompassing the memory chips, the second substrate, and the driving chip; and
external connection terminals mounted to a lower surface of the first substrate.
13. The semiconductor package according to claim 1 , further comprising:
additional memory chips stacked on the first substrate.
14. The semiconductor package according to claim 13 , wherein the additional memory chips are memory chips which belong in a different kind.
15. The semiconductor package according to claim 14 , wherein the memory chips comprise DRAM devices, and the additional memory chips comprise flash memory devices.
16. The semiconductor package according to claim 13 , further comprising:
wires electrically connecting bonding pads of the additional memory chips with the first substrate.
17. The semiconductor package according to claim 16 , wherein the additional memory chips are stacked in a step-like shape such that their bonding pads are exposed.
18. The semiconductor package according to claim 13 , wherein each of the additional memory chips has through vias, and the additional memory chips are stacked such that their through vias are connected with one another.