Shared tracking circuit

1. A system comprising:

a plurality of first memory macros, each one of the plurality of first memory macros comprising a corresponding global control circuit configured to receive a common control signal; and

a first tracking circuit configured to generate the common control signal to be shared by the plurality of first memory macros,

wherein

the first tracking circuit includes at least one of

a first type tracking circuit associated with a row of memory cells of a first memory macro of the plurality of first memory macros;

a second type tracking circuit associated with a column of memory cells of the first memory macro of the plurality of first memory macros;

a decoder tracking circuit associated with decoding circuitry of the first memory macro of the plurality of first memory macros; and

an input-output tracking circuit associated with input-output circuitry of the first memory macro of the plurality of first memory macros.

2. The system of claim 1 , further comprising:

a plurality of second memory macros; and

a second tracking circuit to be shared by the plurality of second memory macros,

wherein

the plurality of first memory macros shares a first clock signal; and

the plurality of second memory macros shares a second clock signal different from the first clock signal.

3. The system of claim 1 , wherein

at least one of the first type tracking circuit associated with a row of memory cells, the second type tracking circuit associated with a column of memory cells, the decoder tracking circuit, or the input-output tracking circuit of the first tracking circuit includes a tracking driver, a tracking line, and a plurality of tracking cells;

the tracking driver corresponds to a driver;

the tracking line corresponds to a line; and

the plurality of tracking cells corresponds to a plurality of cells,

wherein

a driving capability of the tracking driver is related to a driving capability of the driver based on a ratio; and

a number of the plurality of tracking cells is related to a number of the plurality of cells based on the ratio.

4. The system of claim 1 , wherein

at least one of the first type tracking circuit associated with a row of memory cells, the second type tracking circuit associated with a column of memory cells, the decoder tracking circuit, or the input-output tracking circuit of the first tracking circuit includes a tracking driver, a tracking line, and a plurality tracking cells;

the tracking driver corresponds to a driver;

the tracking line corresponds to a line; and

the plurality of tracking cells corresponds to a plurality of cells,

wherein

the line has a first shape, a first resistance value, and a first capacitance value;

the tracking line has a second shape, a second resistance value, and a second capacitance value;

the second shape is different from the first shape; and

the second resistance value is about the same as the first resistance value and/or the second capacitance value is about the same as the first capacitance value.

5. A method for generating a tracking circuit, the method comprising:

identifying a driver and a load of the driver in a circuit to be tracked;

identifying a ratio; and

in a tracking circuit used to track the circuit to be tracked, based on the ratio, identifying a tracking driver corresponding to the driver and a tracking load of the tracking driver.

6. The method of claim 5 , wherein the tracking circuit is shared by a plurality of memory macros.

7. The method of claim 5 , further comprising

identifying a first line corresponding to the load, wherein the line has a first shape; and

generating a second line having a second shape different from the first shape, wherein a resistance of the first line is about the same as a resistance of the second line and/or a capacitance of the first line is about the same as a capacitance of the second line.

8. The method of claim 5 , further comprising

identifying circuit elements coupled with a line driven by the driver, wherein the circuit elements affect a value of the load.

9. The method of claim 5 , wherein

a driving capability of the tracking driver is related to a driving capability of the driver based on the ratio; and

a number of circuit elements of the tracking load is related to a number of circuit elements of the load based on the ratio.

10. The method of claim 9 , wherein

the circuit elements of the load include first transistors; and

the circuit elements of the tracking load include second transistors.

11. The method of claim 5 , wherein

the tracking circuit is selected from a group consisting of a first tracking circuit, a second tracking circuit, a decoder tracking circuit, and an input-output tracking circuit;

the first tracking circuit is associated with a column of memory cells of a memory macro;

the second tracking circuit is associated with a row of memory cells of the memory macro;

the decoder tracking circuit is associated with decoder circuits of the memory macro; and

the input-output tracking circuit is associated with input-output circuits of the memory macro.

12. The method of claim 5 , wherein

the driver is coupled with a line coupling a plurality of first transistors that affect a value of the load;

the tracking driver is coupled with a tracking line coupling a plurality of second transistors that affect a value of the tracking load; and

a size of a second transistor of the plurality of second transistors corresponds to a size of multiple first transistors of the plurality of first transistors.

13. The method of claim 5 , wherein

the driver is coupled with a line coupling a plurality of first transistors that affect a value of the load;

the tracking driver is coupled with a tracking line coupling a plurality of second transistors that affect a value of the tracking load; and

a total size of the plurality of second transistors corresponds to a total size of the plurality of first transistors based on the ratio.

14. A system comprising:

a plurality of memory macros; and

a tracking circuit to be shared by the plurality of memory macros,

wherein

a sub circuit to be tracked in a memory macro of the plurality of memory macros includes a driver, a line, and a load;

a sub tracking circuit of the tracking circuit includes a tracking driver, a tracking line, and a tracking load;

a driving capability of the tracking driver is related to a driving capability of the driver based on a ratio; and

the tracking load is related to the load based on the ratio.

15. The system of claim 14 , wherein

the ratio has a value different from one.

16. The system of claim 14 , wherein

the load is asserted by a plurality of cells; and

the tracking load is asserted by a plurality of tracking cells.

17. The system of claim 14 , wherein

the driver of the sub circuit is configured to drive a plurality of cells;

the tracking driver of the sub tracking circuit is configured to drive a plurality of tracking cells; and

a number of the plurality of tracking cells is related to a number of the plurality of cells based on the ratio.

18. The system of claim 14 , wherein

the driver of the sub circuit is configured to drive a plurality of cells;

the tracking driver of the sub tracking circuit is configured to drive a plurality of tracking cells;

a cell of the plurality of cells includes a plurality of cell transistors;

a tracking cell of the plurality of tracking cells includes a tracking transistor; and

a size of the tracking transistor corresponds to a total size of the plurality of cell transistors.

19. The system of claim 14 , wherein

the driver of the sub circuit is configured to drive a plurality of cells having a plurality of first transistors;

the tracking driver of the sub tracking circuit is configured to drive a plurality of tracking cells having a plurality of second transistors; and

a size of the plurality of the second transistors corresponds to a size of the plurality of the first transistors based on the ratio.

20. The system of claim 14 , wherein

the driver of the sub circuit is configured to drive a plurality of cells having a plurality of first transistors;

the tracking driver of the sub tracking circuit is configured to drive a plurality of tracking cells having a plurality of second transistors; and

a size of a second transistor of the plurality of second transistors corresponds to a size of multiple first transistors of the plurality of first transistors.

21. The system of claim 14 , wherein

the line has a first shape;

the tracking line has a second shape different from the first shape; and

a resistance value of the tracking line is about the same as a resistance value of the line and/or a capacitance value of the tracking line is about the same as a capacitance value of the line.