Systems and methods for loop feedback
View Patent ↗The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing loop feedback in a data processing system.
1. A data processing system, the data processing system comprising:
a loop feedback circuit including:
an equalization circuit operable to equalize a data input to yield a equalizer output, wherein the equalization circuit includes:
a first phase equalizer circuit operable to equalize the data input to yield a first phase equalized output, wherein the first phase equalized output is offset from a defined phase by a first phase offset;
a second phase equalizer circuit operable to equalize the data input to yield a second phase equalized output, wherein the second phase equalized output is offset from the defined phase by a second phase offset; and
a selection circuit operable to select between at least one of a first output derived from the first phase equalized output or a second output derived from the second phase equalized output to be provided as the equalizer output; and
a data detector circuit operable to apply a data detection algorithm to the equalizer output to yield a detected output.
2. The data processing system of claim 1 , wherein the data processing system further comprises:
an analog to digital converter circuit operable to convert an analog input into a series of digital samples provided as the data input synchronized by a sampling clock; and
wherein the loop feedback circuit further comprises:
a sample clock adjustment circuit operable to update the sampling clock based upon a combination of the equalizer output and the detected output.
3. The data processing system of claim 2 , wherein the data processing system further comprises:
a backend processing circuit operable to recover an original data set using the data input.
4. The data processing system of claim 3 , wherein the data detector circuit is a first data detector circuit, the detected output is a first detected output, and the data detection algorithm is a first data detection algorithm, and wherein the backend processing circuit comprises:
a digital finite impulse response circuit operable to equalize the data input to yield a detector input;
a second data detector circuit operable to apply a second data detection algorithm to the detector input to yield a second detected output; and
a data decoder circuit operable to apply a data decode algorithm to a decoder input to yield a decoded output, wherein the decoder input is derived from the second detected output.
5. The data processing system of claim 1 , wherein the data detection algorithm is a first data detection algorithm, wherein the defined phase offset is zero, wherein the first phase offset is a left phase offset, wherein the second phase offset is a right phase offset, and wherein the equalization circuit comprises:
a center phase equalizer circuit operable to equalize the data input to yield a center phase equalized output;
a left phase channel detector circuit operable to apply a second data detection algorithm to the first phase equalized output to yield a left phase detected output, wherein the left phase detected output is the first output derived from the first phase equalized output;
a center phase channel detector circuit operable to apply the second data detection algorithm to the center phase equalized output to yield a center phase detected output, wherein the center phase detected output is the second output derived from the second phase equalized output;
a right phase channel detector circuit operable to apply the second data detection algorithm to the second phase equalized output to yield a right phase detected output; and
wherein the selection circuit operable to provide one of the left phase detected output, the center phase detected output, or the right phase detected output as the equalizer output.
6. The data processing system of claim 5 , wherein the first detection algorithm includes more states than the second detection algorithm.
7. The data processing system of claim 6 , wherein the first detection algorithm is a sixteen state data detection algorithm, and the second detection algorithm is a four state data detection algorithm.
8. The data processing system of claim 5 , wherein the equalization circuit further comprises:
an adaptive Viterbi circuit operable to update edge mean values based at least in part on the center phase detected output and a known input, wherein application of the second data detection algorithm by the center phase channel detector circuit is controlled at least in part by the edge mean values.
9. The data processing systems of claim 8 , wherein the edge mean values are only updated when a possible error event is detected, wherein the possible error event is defined as a path beginning at the divergence between a known data path and a decision data path and ending at re-convergence of the known data path and the decision data path.
10. The data processing system of claim 8 , wherein updating the edge mean values includes calculating a delta K value in accordance with the following equation:
Δ
k
=
∑
i
=
0
L
{
(
y
k
+
i
-
edge
mean
k
+
i
known
data
path
branch
)
2
-
(
y
k
+
i
-
edge
mean
k
+
i
decision
data
path
branch
)
2
}
,
wherein L is the length of the possible error event,
wherein edge mean k+i known data path branch is the expected output along the known data path, and wherein edge mean k+i decision data path branch is the expected output along a decision path of the data detector circuit.
11. The data processing system of claim 10 , wherein the edge mean values are only updated when a value of delta K is less than a threshold value.
12. The data processing system of claim 8 , wherein updating the edge mean values is done in accordance with the following equations:
edge mean k+i known data path branch =edge mean k+i known data path branch +μ( y k+i −edge mean k+i known data path branch ),
edge mean k+i decision data path branch =edge mean k+i decision data path branch −μ( y k+i −edge mean k+i decision data path branch ),
wherein μ is a gain factor, wherein L is the length of the possible error event, wherein edge mean k+i known data path branch is the expected output along the known data path, and wherein
edge mean k+i decision data path branch is the expected output along a decision path of the data detector circuit, y k+i is the center phase detected output.
13. The data processing system of claim 1 , wherein the data processing system is implemented as an integrated circuit.
14. The data processing system of claim 1 , wherein the data processing system is incorporated in a device selected from a group consisting of: a storage device, and a data transmission device.
15. A data processing method, the data processing method comprising:
converting an analog input into a series of digital samples provided as a data input;
equalizing the data input using a left phase equalizer circuit to yield a left phase equalized output, wherein the left phase equalized output is offset from a center phase by a phase offset;
equalizing the data input using a center phase equalizer circuit to yield a center phase equalized output, wherein the center phase equalized output is not offset from the center phase;
applying a second data detection algorithm to the left phase equalized output to yield a left phase detected output;
applying the second data detection algorithm to the center phase equalized output to yield a center phase detected output;
selecting one of the left phase detected output or the center phase detected output as an equalizer output;
applying a first data detection algorithm to the equalizer output to yield a detected output; and
updating a feedback output based upon a combination of the equalizer output and the detected output.
16. The method of claim 15 , wherein the first detection algorithm includes more states than the second detection algorithm.
17. The method of claim 15 , wherein the method further comprises:
updating edge mean values based at least in part on the center phase detected output and a known input, wherein applying the second data detection algorithm by the center phase channel detector circuit is controlled at least in part by the edge mean values.
18. The method of claim 17 , wherein the edge mean values are only updated when a possible error event is detected, wherein the possible error event is defined as a path beginning at the divergence between a known data path and a decision data path and ending at re-convergence of the known data path and the decision data path.
19. The method of claim 17 , wherein updating the edge mean values includes calculating a delta K value in accordance with the following equation:
Δ
k
=
∑
i
=
0
L
{
(
y
k
+
i
-
edge
mean
k
+
i
known
data
path
branch
)
2
-
(
y
k
+
i
-
edge
mean
k
+
i
decision
data
path
branch
)
2
}
,
wherein L is the length of the possible error event,
wherein edge mean k+i known data path branch is the expected output along the known data path, and wherein edge mean k+i decision data path branch is the expected output along a decision path of the data detector circuit.
20. The method of claim 19 , wherein the edge mean values are only updated when a value of delta K is less than a threshold value.
21. The method of claim 17 , wherein updating the edge mean values is done in accordance with the following equations:
edge mean k+i known data path branch =edge mean k+i known data path branch +μ( y k+i −edge mean k+i known data path branch ),
edge mean k+i decision data path branch =edge mean k+i decision data path branch −μ( y k+i −edge mean k+i decision data path branch ),
wherein μ is a gain factor, wherein L is the length of the possible error event, wherein edge mean k+i known data path branch is the expected output along the known data path, and wherein edge mean k+i decision data path branch is the expected output along a decision path of the data detector circuit, y k+i is the center phase detected output.
22. A storage device, the storage device comprising:
a storage medium;
a head assembly disposed in relation to the storage medium and operable to provide a sensed signal corresponding to a data set on the storage;
a read channel circuit including:
an analog to digital converter circuit operable to sample the analog signal derived from the sensed signal to yield a series of digital samples synchronized by a sampling clock;
a loop feedback circuit including:
a state detector based equalization circuit operable to equalize the digital samples to yield a equalizer output, wherein the state detector based equalization circuit includes:
a first means for equalizing the data input to yield a first phase equalized output, wherein the first phase equalized output is offset from a defined phase by a first phase offset;
a second means for equalizing the data input to yield a second phase equalized output, wherein the second phase equalized output is offset from the defined phase by a second phase offset; and
a third means for equalizing the data input to yield a third phase equalized output, wherein the third phase equalized output is offset from the defined phase by a third phase offset.