Dynamic dithering method and apparatus for analog-to-digital converters

1. An analog-to-digital conversion circuit, comprising:

a sample-and-hold amplifier (SHA) configured to sample an analog input signal, add a dither signal to the sampled analog input signal, and produce an analog SHA output signal; and

an analog-to-digital converter (ADC) coupled to the SHA, the ADC configured to convert the analog SHA output signal to a digital ADC output signal;

wherein the SHA includes an adjustment circuit configured to adjust at least a polarity of the dither signal based on the sampled analog input signal such that the analog SHA output signal does not exceed an input voltage range of the ADC.

2. The analog-to-digital conversion circuit of claim 1 , further comprising a dither subtract circuit coupled to the ADC, the dither subtract circuit configured to receive the digital ADC output signal and subtract the dither signal from the digital ADC output signal to produce a digital output signal.

3. The analog-to-digital conversion circuit of claim 1 , wherein the adjustment circuit is configured to adjust the dither signal such that the adjusted dither signal has a negative value when the analog input signal is above a given voltage and the adjusted dither signal has a positive value when the analog input signal is below a given voltage.

4. The analog-to-digital conversion circuit of claim 1 , wherein the adjustment circuit is configured to adjust a magnitude of the dither signal.

5. The analog-to-digital conversion circuit of claim 1 , wherein the SHA comprises a sub-ADC configured to convert the analog input signal to a digital sub-ADC output signal and to provide the digital sub-ADC output signal to the adjustment circuit.

6. An analog-to-digital conversion circuit, comprising:

a sample-and-hold amplifier (SHA) configured to sample an analog input signal, add a dither signal to the sampled analog input signal, and produce an analog SHA output signal; and

an analog-to-digital converter (ADC) coupled to the SHA, the ADC configured to convert the analog SHA output signal to a digital ADC output signal;

wherein the SHA comprises a circuit configured to adjust the dither signal such that the analog SHA output signal does not exceed an input voltage range of the ADC, and wherein the SHA further comprises a sub-ADC configured to convert the analog input signal to a digital sub-ADC output signal by sampling the analog input signal, said digital sub-ADC output signal provided to the circuit configured to adjust the dither signal.

7. The analog-to-digital conversion circuit of claim 6 , further comprising a digital-to-analog converter coupled to the circuit configured to adjust the dither signal, said digital-to-analog converter configured to convert the output of the circuit configured to adjust the dither signal into an analog output signal.

8. The analog-to-digital conversion circuit of claim 7 , further comprising an analog summing circuit configured to add the analog output signal from the digital-to-analog converter to the analog input signal.

9. The analog-to-digital conversion circuit of claim 8 , further comprising an amplifier configured to amplify an output of the summing circuit to produce the analog SHA output signal.

10. The analog-to-digital conversion circuit of claim 8 , further comprising a second digital-to-analog converter coupled to the circuit configured to adjust the dither signal, the second digital-to-analog converter configured to convert the output of the circuit configured to adjust the dither signal into a second analog output signal and to provide the second analog output signal to the analog summing circuit.

11. The analog-to-digital conversion circuit of claim 6 , wherein the sub-ADC and the digital-to-analog converter have an arbitrary number of quantization steps.

12. The analog-to-digital conversion circuit of claim 6 , wherein the circuit configured to adjust the dither signal is configured to adjust the dither signal based on the digital sub-ADC output signal.

13. The analog-to-digital conversion circuit of claim 6 , wherein the circuit configured to adjust the dither signal is configured to adjust a polarity and a magnitude of the dither signal.

14. The analog-to-digital conversion circuit of claim 6 , further comprising a dither subtract circuit coupled to the ADC, the dither subtract circuit configured to receive the digital ADC output signal and subtract the dither signal from the digital ADC output signal to produce a digital output signal.

15. A method of converting an analog input signal to a digital signal, the method comprising:

sampling the analog input signal, said sampling comprising converting the analog input signal to a digital sub-ADC output signal;

providing a dither signal;

adjusting the dither signal based on the digital sub-ADC output signal;

adding the dither signal to the sampled analog input signal and producing an analog output signal; and

converting the analog output signal to a digital output signal using an analog-to-digital converter (ADC);

wherein said adjusting comprises adjusting the dither signal such that the analog output signal does not exceed an input voltage range of the ADC.

16. The method of claim 15 , further comprising subtracting the dither signal from the digital output signal from the ADC.

17. The method of claim 15 , further comprising converting the result of the step of adding the dither signal to the sampled analog input signal to an analog signal.

18. The method of claim 17 , further comprising adding the analog signal to the analog input signal using a summing circuit.

19. The method of claim 18 , further comprising amplifying an output of the summing circuit to produce the analog output signal.

20. The method of claim 15 , wherein said adjusting comprises adjusting the dither signal such that the adjusted dither signal has a negative value when the analog input signal is above a given voltage, and the adjusted dither signal has a positive value when the analog input signal is below a given voltage.

21. The method of claim 15 , wherein said adjusting comprises adjusting a polarity and a magnitude of the dither signal.

22. An analog-to-digital conversion circuit, comprising:

a sample-and-hold amplifier (SHA) configured to sample an analog input signal and produce an analog SHA output signal based on a dither signal and the sampled analog input signal;

an analog-to-digital converter (ADC) configured to convert the analog SHA output signal to a digital ADC output signal; and

a dither subtract circuit configured to receive the digital ADC output signal and subtract the dither signal from the digital ADC output signal to produce a digital output signal.

23. The analog-to-digital conversion circuit of claim 22 , wherein the SHA is configured to adjust a polarity and a magnitude of the dither signal to produce an adjusted dither signal and to produce the SHA output signal based on the adjusted dither signal.

24. The analog-to-digital conversion circuit of claim 22 , wherein the SHA comprises a sub-ADC configured to convert the analog input signal to a digital sub-ADC output signal, wherein the SHA is configured to adjust the dither signal based on the digital sub-ADC output to produce the SHA output signal based on adjusted dither signal.

25. The analog-to-digital conversion circuit of claim 24 , wherein the SHA is configured to adjust the dither signal to produce an adjusted dither signal, and wherein the SHA further comprises:

a first digital-to-analog converter configured to receive the adjusted dither signal and convert the adjusted dither signal into a first analog signal;

a second digital-to-analog converter configured to receive the adjusted dither signal and convert the adjusted dither signal into a second analog signal; and

an analog summing circuit configured to add the analog input signal, the first analog signal, the second analog signal.

26. The analog-to-digital conversion circuit of claim 22 , wherein the SHA is configured to adjust the dither signal such that the analog SHA output signal stays within an input voltage range of the ADC.