Low-power, low-latency architecture for telecom and datacom multiplexers and demultiplexers
View Patent ↗Described herein are systems and methods for reducing power consumption, latency, and chip complexity in a datacom/telecom multiplexer and demultiplexer. Adding a high frequency analog domain data path around or in place of a standard digital core data path allows the elimination of the demultiplexing and multiplexing stages required to drop the data rate of data streams down to that required for a standard digital core. Latency is also reduced due to the higher operating frequency of sequential elements required for data operations. The digital core can be powered down when not in use, and can be activated when necessary.
1. A circuit, comprising:
a set of clock data recovery circuits and demultiplexers that receives data streams;
a digital core data path with an analog multiplexer and demultiplexer; and
an analog domain data path that bypasses the digital core data path and sends the data streams to a multiplexer with a higher data rate data output, wherein in response to the analog domain data path being used in a normal mode, the digital core data path is powered down.
2. The circuit of claim 1 , wherein the analog domain data path is implemented using at least one of static CMOS, SCL, ECL, or BiCMOS.
3. The circuit of claim 1 , wherein the analog domain data path includes a FIFO structure that transitions data from their respective recovered clock domains to a data output clock domain.
4. The circuit of claim 3 , wherein the FIFO structure absorbs wander between receive and transmit channels, wherein the FIFO structure is operated at a low divide ratio.
5. The circuit of claim 1 , wherein power is reduced in response to clock and data gating based on a mode of the analog domain data path.
6. The circuit of claim 3 , wherein a data stream to the digital core data path is tapped and demultiplexed after passing through the FIFO structure.
7. The circuit of claim 1 , wherein a latency of the circuit is decreased based on a high frequency sequential data operation.
8. The circuit of claim 1 , further comprising a diagnostic component on the digital core data path that performs chip and link diagnostics on a data stream.
9. The circuit of claim 1 , wherein there are a higher number of input data streams than output data streams.
10. The circuit of claim 1 , wherein the analog domain data path is surrounded by the analog multiplexer and demultiplexer.
11. The circuit of claim 1 , wherein a non-power of two data path mapping logic is included in the analog domain data path and non-power of two multiplexing is included in the analog multiplexer in place of a memory based gearbox in a digital domain.
12. A circuit, comprising:
a set of clock data recovery circuits and demultiplexers that receives input data streams;
a digital core data path with an analog multiplexer and demultiplexer; and
an analog domain data path that bypasses the digital core data path and sends the data streams to a multiplexer that outputs the data streams at a lower data rate than the input data streams, wherein in response to the analog domain data path being used in a normal mode, the digital core data path is powered down.
13. The circuit of claim 12 , wherein the digital core data path is activated anda data stream is passed to a deskew component in a digital core in response to a deskew mode bit being turned on.
14. The circuit of claim 12 , wherein the analog domain data path is implemented using at least one of low power static CMOS, MOS, or bipolar CMOS.
15. The circuit of claim 12 , wherein the analog domain data path includes a FIFO structure that transitions data streams from respective recovered clock domains to a data output clock domain, and wherein the FIFO structure is operated at a low divide ratio of the input data to add a minimum amount of skew between receive channels while treating all receive channels independently.
16. The circuit of claim 15 , wherein a data stream to the digital core data path is tapped and demultiplexed after passing through the FIFO structure.
17. The circuit of claim 12 , further comprising a diagnostic component on the digital core data path that performs chip and link diagnostics on a data stream.
18. The circuit of claim 12 , wherein there are a higher number of output data streams than input data streams.
19. The circuit of claim 12 , wherein non-power of two demultiplexing is included in the analog demultiplexer and non-power of two data path mapping logic is included in the analog domain data path in place of a memory based gearbox in a digital domain.
20. A method comprising:
receiving a first set of data streams at a set of clock data recovery circuits and demultiplexers;
directing the first set of data streams through an analog domain data path;
passing a data stream that requires digital processing above a predefined threshold to a digital core data path, wherein the digital core data path is powered down when not in use; and
outputting a second set of data streams from the analog domain data path and a multiplexer wherein a data rate of the second set of data streams is different than a data rate of the first set of data streams.