INTEGRATED CIRCUIT WITH CALIBRATED PULLING EFFECT CORRECTION
A calibration circuit includes a combinational gate configured to receive a voltage-controlled oscillator (VCO) output signal and a selected reference signal to detect a phase difference between the VCO output signal and the selected reference signal and generate an output binary signal, in which the VCO output signal has one or more unwanted frequency components. The calibration circuit also includes a loop filter configured to filter the output binary signal and generate a filtered calibration signal. The calibration circuit also includes an analog-to-digital converter configured to convert the filtered calibration signal from the analog domain to the digital domain and generate a converted calibration signal. The calibration circuit also includes a processor configured to compute the converted calibration signal and determine components of a baseband signal that cancels the one or more unwanted frequency components of the VCO output signal.
1 . A calibration circuit for calibrating a reduction in interference from a pulling signal having one or more unwanted frequency components, comprising:
a combinational gate coupled to an output of a voltage-controlled oscillator (VCO), the combinational gate configured to receive a VCO output signal and a selected reference signal to detect a phase difference between the VCO output signal and the selected reference signal and generate an output binary signal, wherein the VCO output signal comprises the one or more unwanted frequency components of the pulling signal;
a loop filter coupled to an output of the VCO, the loop filter configured to filter the output binary signal and generate a filtered calibration signal;
an analog-to-digital converter coupled to an output of the loop filter, the analog-to-digital converter configured to convert the filtered calibration signal from the analog domain to the digital domain and generate a converted calibration signal; and
a processor coupled to an output of the analog-to-digital converter, the processor configured to compute the converted calibration signal and determine components of a baseband signal that corrects for the one or more unwanted frequency components of the VCO output signal.
2 . The calibration circuit of claim 1 , further comprising:
a phase-locked loop (PLL) coupled to an input of the combinational gate, the PLL configured to receive a reference frequency signal and output an output oscillator signal proportionate to the reference frequency signal,
wherein the selected reference signal is based on a selection between the output oscillator signal and the reference frequency signal.
3 . The calibration circuit of claim 2 , wherein the PLL comprises:
a phase frequency detector (PFD) configured to detect a difference in phase and frequency between the reference frequency signal and output oscillator signal and generate a PFD signal; and
a wideband low-pass filter coupled to an output of the PFD, the wideband low-pass filter configured to filter the PFD signal and output a filtered PFD signal.
4 . The calibration circuit of claim 3 , wherein the PLL comprises:
a ring oscillator coupled to an output of the wideband low-pass filter, the ring oscillator configured to receive the filtered PFD signal and generate the output oscillator signal that is 1/N times the VCO output signal, where N is a positive integer,
wherein the output oscillator signal is directly proportionate to the VCO output signal.
5 . The calibration circuit of claim 4 , further comprising:
a frequency divider inserted in a feedback loop from the ring oscillator to the PFD and configured to increase the output oscillator signal by N times the reference frequency signal, where N is a positive integer.
6 . The calibration circuit of claim 4 , further comprising:
a sigma-delta modulator inserted in a feedback loop from the ring oscillator to the PFD and configured to increase the output oscillator signal by a fractional divide ratio of N/N+1 times the reference frequency signal, where N is a positive integer.
7 . The calibration circuit of claim 1 , wherein the VCO output signal comprises second-order frequency components of a transmitted baseband signal.
8 . The calibration circuit of claim 7 , wherein the second-order frequency components of the transmitted baseband signal are greater than a magnitude threshold.
9 . The calibration circuit of claim 1 , wherein the calibration circuit is operable during a calibration state to generate the baseband signal that varies the VCO output signal.
10 . The calibration circuit of claim 1 , wherein the VCO output signal is output from a phase-locked loop (PLL).
11 . The calibration circuit of claim 1 , wherein the loop filter is a first-order low-pass filter.
12 . The calibration circuit of claim 1 , wherein the processor is a digital signal processor.
13 . An apparatus for calibrating a reduction in interference from a pulling signal having one or more unwanted frequency components, comprising:
means for receiving a voltage-controlled oscillator (VCO) output signal and a selected reference signal to detect a phase difference between the VCO output signal and the selected reference signal and generating an output binary signal, wherein the VCO output signal comprises the one or more unwanted frequency components of the pulling signal;
means for filtering the output binary signal and generating a filtered calibration signal;
means for converting the filtered calibration signal from the analog domain to the digital domain and generating a converted calibration signal; and
means for computing the converted calibration signal and determining components of a baseband signal that corrects for the one or more unwanted frequency components of the VCO output signal.
14 . The apparatus of claim 13 , further comprising:
means for receiving a reference frequency signal and outputting an output oscillator signal proportionate to the reference frequency signal,
wherein the selected reference signal is based on a selection between the output oscillator signal and the reference frequency signal.
15 . The apparatus of claim 14 , wherein the means for outputting the output oscillator signal comprises:
means for detecting a difference in phase and frequency between the reference frequency signal and output oscillator signal and generating a PFD signal; and
means for filtering the PFD signal and outputting a filtered PFD signal.
16 . The apparatus of claim 15 , wherein the means for outputting the output oscillator signal comprises:
means for receiving the filtered PFD signal and generating the output oscillator signal that is 1/N times the VCO output signal, where N is a positive integer,
wherein the output oscillator signal is directly proportionate to the VCO output signal.
17 . The apparatus of claim 16 , further comprising:
means for adjusting the output oscillator signal by N times the reference frequency signal, where N is a positive integer.
18 . The apparatus of claim 16 , further comprising:
means for adjusting the output oscillator signal by a fractional divide ratio of N/N+1 times the reference frequency signal, where N is a positive integer.