Serializer/deserializer apparatus with loopback configuration and methods thereof
View Patent ↗The present invention is directed to integrated circuits. In a specific embodiment, high frequency signals from an equalizer is directly connected to a first pair of inputs of a sense amplifier. The sense amplifier also has a second pair of inputs, which can be selectively coupled to output signals from a DAC or high frequency loopback signals. There are other embodiments as well.
1. An integrated circuit device comprising:
an equalizer configured to output a first input voltage and a second input voltage, the first input voltage carrying serial data at a frequency of at least 1 GHz, the second input voltage carrying serial data at a frequency of at least 1 GHz;
a digital to analog converter configured to output a first DAC signal and a second DAC signal, the first DAC signal and the second DAC signals being characterized by a frequency of less than 0.5 GHz;
a loopback driver being configured to output a first loopback signal and a second loopback signal, the first loopback signal and the second loopback signal being characterized by a frequency of at least 1 GHz;
a first switch coupled to the first loopback signal, the first switch comprising a first filter;
a second switch coupled to the second loopback signal, the second switch comprising a second filter; and
a sense amplifier having first input coupled to the first input voltage, a second input coupled to the second input voltage, a third input coupled to the first loopback signal through the first switch and the first DAC signal, a fourth input coupled to the second loopback signal through the second switch and the second DAC signal.
2. The device of claim 1 wherein the first input voltage and the second voltage are a differential pair.
3. The device of claim 1 further comprising a de-multiplexer coupled to an output of the sense amplifier.
4. The device of claim 1 wherein the first reference signal is characterized by a frequency of at least 28 GHz.
5. The device of claim 1 wherein:
the integrated circuit device is configured to operate in a data mode and a loopback mode;
in data mode, the sense amplifier is configured to receive at least the first input voltage and the first DAC signal, the first switch being turned off;
in loopback mode, the sense amplifier is configured to receive at least the loopback signal, the first switch being turn on.
6. The device of claim 1 wherein the first switch comprises a transmission gate.
7. The device of claim 1 wherein the first filter comprises a first capacitor, the first capacitor is characterized by a capacitance of about 1 pF to 10 pF.
8. The device of claim 1 wherein the first filter is a low-pass filtering capacitor.
9. The device of claim 1 wherein the first switch comprises a transmission gate configured in parallel to the first filter.
10. The device of claim 1 wherein the sense amplifier receives a first clock signal and a second clock signal.
11. The device of claim 1 the sense amplifier is configured to compare the first input voltage to the first loopback signal.
12. The device of claim 1 wherein the DAC comprises two 8-bit converters.
13. An integrated circuit device comprising:
an equalizer configured to output a first input voltage carrying serial data at a frequency of at least 1 GHz;
a digital to analog converter configured to output a first DAC signal characterized by a frequency of less than 0.5 GHz;
a loopback driver being configured to output a first loopback signal, the first loopback signal being characterized by a frequency of at least 1 GHz;
a first switch coupled to the first loopback signal, the first switch comprising a first filter; and
a sense amplifier having first input coupled to the first input voltage and a second input coupled to the first loopback signal through the first switch and the first DAC signal;
wherein:
the integrated circuit device is configured to operate in a data mode and a loopback mode;
in data mode, the sense amplifier is configured to receive at least the first input voltage and the first DAC signal, the first switch being turned off.
14. The device of claim 13 wherein the first filter comprises a low-pass filtering capacitor.
15. The device of claim 13 further comprising clock coupled to the sense amplifier.
16. The device of claim 13 further comprising a de-multiplexer.
17. The device of claim 13 wherein the equalizer is directly couple to the sense amplifier.
18. The device of claim 13 further comprising a serial to parallel converter coupled to the sense amplifier.
19. The device of claim 13 further wherein the first loopback signal is received from a transmitter.
20. A SerDes apparatus comprising:
a transmitting circuit;
a receiving circuit, the receiving circuit comprising:
an equalizer configured to output a first input voltage and a second input voltage, the first input voltage carrying serial data at a frequency of at least 1 GHz, the second input voltage carrying serial data at a frequency of at least 1 GHz;
a digital to analog converter configured to output a first DAC signal and a second DAC signal, the first DAC signal and the second DAC signals being characterized by a frequency of less than 0.5 GHz;
a loopback driver being configured receiving a first loopback signal from the transmitting circuit and to output the first loopback signal and a second loopback signal;
a first switch coupled to the first loopback signal, the first switch comprising a first filter;
a second switch coupled to the second loopback signal, the second switch comprising a second filter; and
a sense amplifier having first input coupled to the first input voltage, a second input coupled to the second input voltage, a third input coupled to the first loopback signal through the first switch and the first DAC signal, a fourth input coupled to the second loopback signal through the second switch and the second DAC signal.