Apparatus and method for reconstructing a bit sequence with preliminary correction

1. A method for reconstructing a physically uncloneable function (PUF) A for use in an electronic device, the method comprising:

generating a potentially erroneous PUF A t ;

performing a preliminary correction of the potentially erroneous PUF A t by means of a stored correction vector Delta t-1 , to obtain a preliminarily corrected PUF B t ;

reconstructing the PUF A from the preliminarily corrected PUF B t by means of an error correction algorithm;

testing to determine whether the PUF A has been reconstructed correctly; and

re-performing the reconstruction of the PUF A without performing a preliminary correction of the potentially erroneous PUF A t if the testing determines the PUF A was incorrectly reconstructed.

2. The method as claimed in claim 1 , wherein reconstructing the PUF A from the preliminarily corrected PUF B t by means of an error correction algorithm comprises:

applying the error correction algorithm to the preliminarily corrected PUF B t to obtain an error vector e t ; and

XORing the preliminarily corrected PUF B t and the error vector e t .

3. The method as claimed in claim 2 , wherein the error correction algorithm is an ECC algorithm.

4. The method as claimed in claim 2 , wherein a current correction vector Delta t is calculated by XORing the stored correction vector Delta t-1 and the error vector e t .

5. The method as claimed in claim 4 , further comprising storing the current correction vector Delta t as a new correction vector in an error register, the new correction vector being used as the correction vector Delta t-1 during a subsequent PUF reconstruction.

6. The method as claimed in claim 1 , wherein the length of the potentially erroneous PUF A t is in a range from 64 bits to 6000 bits.

7. The method as claimed in claim 1 , wherein an average bit error rate of the potentially erroneous PUF A t is in a range from 0.3% to 25%.

8. The method as claimed in claim 1 , wherein the length of the PUF A is in a range from 64 bits to 6000 bits.

9. The method as claimed in claim 1 , wherein the potentially erroneous PUF A t is generated by a transistor-based method.

10. The method as claimed in claim 1 , wherein the correction vector Delta t-1 is stored in a nonvolatile read only memory.

11. The method as claimed in claim 1 , wherein the length of the correction vector Delta t-1 is in a range from 64 bits to 6000 bits.

12. The method as claimed in claim 1 , further comprising producing a cryptographic key from the PUF A.

13. The method as claimed in claim 12 , further comprising using the cryptographic key for encryption with block encryption or stream encryption.

14. The method as claimed in claim 1 , wherein the potentially erroneous PUF A t and the correction vector Delta t-1 are processed on a segment-by-segment basis in segments of equal length.

15. An apparatus for reconstructing a physically uncloneable function (PUF) A, comprising:

an element configured to generate a potentially erroneous PUF A t ;

a memory configured to store a correction vector Delta t-1 ;

a first computation unit configured to perform a preliminary correction of the PUF A t by means of a stored correction vector Delta t-1 , to obtain a preliminarily corrected PUF B t ; and a second computation unit configured to reconstruct the PUF A from the preliminarily corrected PUF B t by means of an error correction algorithm, test to determine whether the PUF A has been reconstructed correctly, and re-perform the reconstruction of the PUF A without performing a preliminary correction of the potentially erroneous PUF A t if the testing determines the PUF A was incorrectly reconstructed.

16. The apparatus as claimed in claim 15 , wherein the second computation unit is configured to reconstruct the PUF A from the preliminarily corrected PUF B t by applying the error correction algorithm to the preliminarily corrected PUF B t to obtain an error vector e t , and XORing the preliminarily corrected PUF B t and the error vector e t .

17. The apparatus as claimed in claim 15 , wherein the first and second computation units are part of the same integrated circuit.

18. The apparatus as claimed in claim 15 , wherein the apparatus is a chip card or an RFID device.