Operating method of memory system including NAND flash memory, variable resistance memory and controller

1. An operating method of a memory system, the memory system including a NAND flash memory, a resistance variable memory, and a controller controlling the NAND flash memory and the resistance variable memory, the method comprising:

receiving data;

programming the received data in the NAND flash memory when the received data is at least a super page of data;

programming the received data in the resistance variable memory when the received data is not the super page of data; and

programming data accumulated in the resistance variable memory in the NAND flash memory when the data accumulated in the resistance variable memory is the super page of data,

wherein the super page of data is an entirety of data that is programmable in memory cells connected to a same word line of the NAND flash memory.

2. The operating method of claim 1 , wherein two or more bits of data are programmable in each of the memory cells connected to the same word line of the NAND flash memory, and wherein the super page of data includes two or more bits being programmed at each of the memory cells connected to the same word line.

3. The operating method of claim 2 , wherein the NAND flash memory includes adjacent memory cells connect to a word line adjacent the same word line, and wherein the super page of data further includes at least one bit being programmed at each of the adjacent memory cells.

4. The operating method of claim 3 , wherein a program operation is performed in sequence with respect to the same word line and the adjacent word line; and wherein the super page of data further comprises first data being programmed at the memory cells connected to the same word line and second data being programmed at the adjacent memory cells connected to the adjacent word line, the first and second data being required until programming of the memory cells connected to the same word line is completed.

5. The operating method of claim 1 , wherein the programming the received data in the resistance variable memory comprises:

generating first data by adding a first parity to the received data; and

programming the first data at the resistance variable memory, the generating and the programming being performed by the controller.

6. The operating method of claim 5 , wherein the programming the first data in the resistance variable memory comprises:

generating second data by adding a second parity to the first data; and

programming the second data, the generating and the programming the second data being performed by the resistance variable memory.

7. The operating method of claim 6 , wherein the programming the accumulated data in the NAND flash memory comprises:

removing the second parity from accumulated data of the second data; and

programming the data, from which the second parity is removed, in the NAND flash memory, the removing of the second parity being performed by the resistance variable memory.

8. The operating method of claim 1 , wherein the programming the received data in the NAND flash memory comprises:

generating third data by adding a second parity to the received data; and

programming the third data, the generating and the programming being performed by the resistance variable memory.

9. The operating method of claim 8 , wherein the programming the accumulated data in the NAND flash memory comprises:

removing the second parity from accumulated data of the third data being performed by the resistance variable memory;

adding a first parity to the data, from which the second parity is removed by the controller; and

programming the first parity-added data in the NAND flash memory.

10. The operating method of claim 1 , wherein the resistance variable memory is a phase change memory.

11. The operating method of claim 1 , wherein the resistance variable memory has over-write functionality.

12. The operating method of claim 1 , wherein physical and logical address systems of the resistance variable memory are the same.

13. The operating method of claim 1 , wherein the resistance variable memory and the NAND flash memory communicate with the controller via a common bus.

14. The operating method of claim 1 , wherein the resistance variable memory supports a plurality of numbers of program with respect to memory cells of the resistance variable memory connected to a word line.

15. An operating method of a memory system which includes a NAND flash memory, a resistance variable memory, and a controller controlling the NAND flash memory and the resistance variable memory, where the NAND flash memory is configured to store N bits of data per memory cell, and N pages of data per word line of each memory block, and where N is two or more, the method comprising:

receiving data;

programming the received data in the NAND flash memory when the received data is at least N pages of data;

programming the received data in the resistance variable memory when the received data is less than N pages of data; and

programming accumulated data programmed in the resistance variable memory in the NAND flash memory when the accumulated data is at least N pages of data.

16. The operating method of claim 15 , wherein the resistance variable memory is a random access memory having over-write functionality.

17. The operating method of claim 15 , wherein the resistance variable memory is a phase change random access memory (PRAM).

18. The operating method of claim 15 , wherein the programming the input data in the resistance variable memory comprises:

generating first data by adding a first parity to the input data; and

programming the first data in the resistance variable memory, the generating and the programming being performed by the controller.

19. The operating method of claim 18 , wherein the programming the first data in the resistance variable memory comprises:

generating second data by adding a second parity to the first data; and

programming the second data, the generating and the programming the second data being performed by the resistance variable memory.

20. An operating method of a memory system which includes a NAND flash memory, a resistance variable memory, and a controller controlling the NAND flash memory and the resistance variable memory, the method comprising:

receiving data;

programming the received data in the resistance variable memory; and

programming a super page of data among data accumulated in the resistance variable memory in NAND flash memory when a free capacity of the resistance variable memory reaches a threshold value,

wherein the super page of data is an entirety of data that is programmable in memory cells of the NAND flash memory connected to a same word line of the NAND flash memory.