Semiconductor device and method of manufacturing the device
A first first-conductivity-type impurity region ( 4 ) is provided in an upper portion of a semiconductor layer ( 102 ) around a trench ( 12 ). A gate electrode ( 8 ) is provided on a sidewall surface of the trench ( 12 ), and on the semiconductor layer ( 102 ) around the trench ( 12 ) with a gate insulating film ( 11 ) interposed therebetween. A second-conductivity-type impurity region ( 50 ) and a second first-conductivity-type impurity region ( 51 ) are interposed between a portion of the gate electrode ( 8 ) around the trench ( 12 ) and the first first-conductivity-type impurity region ( 4 ) sequentially on the first first-conductivity-type impurity region ( 4 ).
1. A semiconductor device, comprising:
a substrate having a semiconductor layer on a principal surface thereof;
a trench provided in the semiconductor layer;
a first first-conductivity-type impurity region provided in an upper portion of the semiconductor layer around the trench;
a gate insulating film provided on a sidewall surface of the trench and on the portion of the semiconductor layer around the trench;
a gate electrode provided on a portion of the gate insulating film inside the trench, and on the gate insulating film on the portion of the semiconductor layer around the trench; and
another electrode directly contacting the first first-conductivity-type impurity region, wherein:
a second-conductivity-type impurity region and a second first-conductivity-type impurity region are interposed around the trench between a portion of the gate electrode and the first-first-conductivity-type impurity region, and are formed sequentially on the first first-conductivity-type impurity region.
2. The device of claim 1 , wherein
a side surface of the second-conductivity-type impurity region opposite to the trench is surrounded by the first first-conductivity-type impurity region.
3. The device of claim 1 , wherein
side surfaces of the second-conductivity-type impurity region and the second first-conductivity-type impurity region opposite to the trench are substantially flush with each other, and are exposed from the first first-conductivity-type impurity region.
4. The device of claim 3 , wherein
the side surfaces of the second-conductivity-type impurity region and the second first-conductivity-type impurity region opposite to the trench are covered by an insulating film together with the gate electrode.
5. The device of claim 3 , wherein
the side surfaces of the second-conductivity-type impurity region and the second first-conductivity-type impurity region opposite to the trench are covered by an insulating sidewall spacer.
6. The device of claim 3 , wherein
the side surfaces of the second-conductivity-type impurity region and the second first-conductivity-type impurity region opposite to the trench are substantially flush with a side surface of the gate electrode at the portion around the trench.
7. The device of claim 1 , further comprising:
a channel layer provided on a surface of the semiconductor layer which is the sidewall surface of the trench.
8. The device of claim 1 , wherein
the second first-conductivity-type impurity region is part of the channel layer provided on the sidewall surface of the trench and on the portion of the semiconductor layer around the trench.
9. The device of claim 8 , wherein
a portion of the channel layer, which will be the second first-conductivity-type impurity region, is depleted by coming into contact with the second-conductivity-type impurity region.
10. The device of claim 1 , wherein
the another electrode is spaced apart from the second-conductivity-type impurity region.
11. The device of claim 10 , further comprising:
an interlayer insulating film provided to cover the gate electrode, wherein
an opening, in which the another electrode is formed, is provided in the interlayer insulating film.
12. The device of claim 1 , wherein
the semiconductor layer is made of silicon carbide.
13. The device of claim 12 , wherein
the substrate is a silicon carbide substrate, and
the principal surface of the substrate is a silicon surface.
14. A method of manufacturing a semiconductor device, the method comprising:
preparing a substrate having a semiconductor layer on a principal surface thereof;
forming a first first-conductivity-type impurity region in an upper portion of the semiconductor layer;
forming a second-conductivity-type impurity region on the first first-conductivity-type impurity region;
forming a second first-conductivity-type impurity region on the second-conductivity-type impurity region;
forming a trench in the semiconductor layer;
forming a gate insulating film on a sidewall surface of the trench and on a portion of the semiconductor layer around the trench;
forming a gate electrode on a portion of the gate insulating film inside the trench, and on the gate insulating film on the portion of the semiconductor layer around the trench; and
forming another electrode on the first first-conductivity-type impurity region such that the electrode directly contacts the first first-conductivity-type impurity region, wherein:
the second-conductivity-type impurity region and the second first-conductivity-type impurity region are interposed around the trench between a portion of the gate electrode and the first first-conductivity-type impurity region.
15. The method of claim 14 , wherein
the second-conductivity-type impurity region is formed so that a side surface of the second-conductivity-type impurity region is surrounded by the first first-conductivity-type impurity region.
16. The method of claim 14 , further comprising:
after the forming the trench, removing the second-conductivity-type impurity region and the second first-conductivity-type impurity region other than portions around the trench, wherein
the second-conductivity-type impurity region is formed to cover an upper surface of the first first-conductivity-type impurity region.
17. The method of claim 16 , further comprising:
after the removing the second-conductivity-type impurity region and the second first-conductivity-type impurity region, covering side surfaces of the second-conductivity-type impurity region and the second first-conductivity-type impurity region opposite to the trench with an insulating film together with the gate electrode.
18. The method of claim 16 , further comprising:
after the removing the second-conductivity-type impurity region and the second first-conductivity-type impurity region, covering side surfaces of the second-conductivity-type impurity region and the second first-conductivity-type impurity region opposite to the trench with an insulating sidewall spacer.
19. The method of claim 16 , wherein
in the removing the second-conductivity-type impurity region and the second first-conductivity-type impurity region, the second-conductivity-type impurity region and the second first-conductivity-type impurity region are removed using a mask for patterning the gate electrode.
20. The method of claim 14 , wherein
the forming the second first-conductivity-type impurity region is performed by forming a channel layer including a portion, which will be the second first-conductivity-type impurity region, on the sidewall surface of the trench and on the portion of the semiconductor layer around the trench, between the forming the trench and the forming the gate insulating film.