IP Library Granted Patent US 9,459,648
Granted Patent B2
US 9,459,648 · App. 13/814,485 · Granted Oct 4, 2016

AC coupled single-ended LVDS receiving circuit comprising low-pass filter and voltage regulator

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Quick Facts
Patent No.
US 9,459,648
App. No.
13/814,485
Granted
Oct 4, 2016
Kind
B2
Abstract

A receiving circuit is provided that can accurately detect a clock signal that has a single phase and a small amplitude. A receiving circuit includes an AC coupled circuit 22 that creates an AC coupling between a first end and a second end, a low-pass filter circuit 23, 25 that produces a third signal by applying a low-pass filtering on a second signal that is produced on the second end in response to a first signal that is applied to the first end, and a comparator 21 that inputs the second signal and the third signal.

Claims (26)

1. A receiving circuit comprising:

an AC-coupled circuit configured to create an AC coupling between a first end and a second end;

a low-pass filter circuit configured to, in response to a first signal that is applied to the first end, apply a low-pass filtering on a second signal that is produced on the second end to produce a reference signal;

a comparator configured to receive an input of the second signal and the reference signal to produce an output signal; and

a voltage-regulating circuit configured to match a voltage value of the second signal to a common-mode voltage rating of the comparator, wherein the voltage regulating circuit includes a series of resistors disposed between a power source voltage and a ground voltage.

2. The receiving circuit according to claim 1 , wherein the comparator is a low voltage differential signaling (LVDS) receiver.

3. The receiving circuit according to claim 1 , wherein the series of resistors comprises:

a first resistor connected between the power source voltage and a first input end of the LVDS receiver,

a second resistor connected between the first input end and a second input end of the LVDS receiver, and

a third resistor element connected between the second input end and the ground voltage.

4. The receiving circuit according to claim 1 , wherein the AC coupled circuit includes a capacitive element.

5. The receiving circuit according to claim 1 , wherein the low-pass filter circuit includes a resistor element and a capacitive element.

6. The receiving circuit according to claim 1 , wherein the AC coupled circuit includes a transformer.

7. A signal transmitting circuit, comprising:

a single-phase transmitting wiring;

a damping resistor interposed in the transmitting wiring;

an AC-coupled circuit configured to create an AC coupling between a first end and a second end, the first end connected to a receiving side of the transmitting wiring;

a low-pass filter circuit configured to, in response to a first signal that is applied to a first end, apply a low-pass filtering on a second signal that is produced on the second end to produce a reference signal;

a comparator configured to receive an input of the second signal and the reference signal to produce an output signal; and

a voltage-regulating circuit configured to match a voltage value of the second signal to a common-mode voltage rating of the comparator, wherein the voltage regulating circuit includes a series of resistors disposed between a power source voltage and a ground voltage.

8. The signal transmitting circuit according to claim 7 , wherein the comparator is a low voltage differential signaling (LVDS) receiver.

9. A signal receiving method, comprising the steps of:

extracting AC components from a received signal;

adding the AC components with a voltage regulating circuit to produce a first voltage signal that matches a common-mode voltage rating of a comparator, wherein the voltage regulating circuit includes a series of resistors disposed between a power source voltage and a ground voltage;

applying a low-pass filtering on the first voltage signal to produce a reference voltage signal; and

comparing the first voltage signal and the reference voltage signal at the comparator to produce an output signal.

Assignments (4)
ASSIGNMENT OF INTELLECTUAL PROPERTY SECURITY AGREEMENTS Recorded Dec 12, 2025
From: MS PRIVATE CREDIT ADMINISTRATIVE SERVICES LLC
To: MGG INVESTMENT GROUP LP
Reel/Frame 073959/0584 →
SECURITY INTEREST Recorded Mar 20, 2024
From: GRASS VALLEY CANADA; GRASS VALLEY LIMITED
To: MS PRIVATE CREDIT ADMINISTRATIVE SERVICES LLC
Reel/Frame 066850/0869 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 17, 2021
From: GVBB HOLDINGS S.A.R.L.
To: GRASS VALLEY CANADA
Reel/Frame 056100/0612 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2013
From: KANAMARU, HIROKI
To: GVBB HOLDINGS S.A.R.L.
Reel/Frame 030402/0846 →