Data processing device and data processing method
View Patent ↗The present invention relates to a data processing device and a data processing method capable of improving the resistance to data error. In a case where an LDPC code having a code length of 4,320 bits is mapped into 16 signal points, when a code bit of 4×2 bits and the (#i+1)-th bit from the most significant bit of symbol bits of 4×2 bits of two consecutive symbols are bits b#i and y#i, a demultiplexer performs an interchange process in which b 0 is allocated to y 0 , b 1 is allocated to y 4 , b 2 is allocated to y 1 , b 3 is allocated to y 6 , b 4 is allocated to y 2 , b 5 is allocated to y 5 , b 6 is allocated to y 3 , and b 7 is allocated to y 7 for an LDPC code having a coded rate of 1/2, and b 0 is allocated to y 0 , b 1 is allocated to y 4 , b 2 is allocated to y 5 , b 3 is allocated to y 2 , b 4 is allocated to y 1 , b 5 is allocated to y 6 , b 6 is allocated to y 3 , and b 7 is allocated to y 7 for an LDPC code having a coded rate of 7/12, 2/3, and 3/4. The present invention, for example, can be applied to a transmission system transmitting an LDPC code and the like.
1. A data processing device comprising:
an interchange means that interchanges code bits of mb bits in accordance with an allocation rule used for allocating the code bits of an LDPC code to symbol bits representing a symbol and sets code bits after interchange as the symbol bits in a case where the code bits of the LDPC (low density parity check) code having a code length of N bits are written in a column direction of a storage means storing the code bits in a row direction and the column direction, the m bits of the code bits of the LDPC code read in the row direction are set as one symbol, a predetermined positive integer is set as b, the storage means stores the mb bits in the row direction and stores N/(mb) bits in the column direction, the code bits of the LDPC code are written in the column direction of the storage means and then are read in the row direction, and the code bits of the mb bits read in the row direction of the storage means form b symbols,
wherein the LDPC code is an LDPC code having a code length N of 4,320 bits,
wherein the allocation rule is a rule that sets groups acquired by grouping the code bits of the mb bits in accordance with an error probability as code bit groups and groups acquired by grouping the symbol bits of the mb bits in accordance with an error probability as symbol bit groups and defines a group set that is a combination of the code bit group of the code bits and the symbol bit group of the symbol bits to which the code bits of the code bit group are allocated and the bit numbers of the code bits and the symbol bits of each one of the code bit group and the symbol bit group of the group set,
wherein, in a case where the m bits are four bits, the integer b is two, and four bits of the code bits are mapped into one of 16 signal points that are determined in 16 QAM as one symbol, the code bits of 4×2 bits are grouped into three code bit groups, and the symbol bits of 4×2 bits are grouped into two symbol bit groups,
wherein, in the allocation rule, allocation of one bit of the code bits of the code bit group of which the error probability is the best to one bit of the symbol bits of the symbol bit group of which the error probability is the best, allocation of two bits of the code bits of the code bit group of which the error probability is second best to two bits of the symbol bits of the symbol bit group of which the error probability is the best, allocation of one bit of the code bits of the code bit group of which the error probability is second best to one bit of the symbol bits of the symbol bit group of which the error probability is second best, allocation of one bit of the code bits of the code bit group of which the error probability is third best to one bit of the symbol bits of the symbol bit group of which the error probability is the best, and allocation of three bits of the code bits of the code bit group of which the error probability is third best to three bits of the symbol bits of the symbol bit group of which the error probability is second best are defined,
wherein a coded rate of the LDPC code having a code length of 4,320 bits is 1/2,
wherein a parity check matrix of the LDPC code is configured by arranging elements of 1's of an information matrix that is determined by a parity check matrix initial value table representing positions of elements of 1's of the information matrix of the parity check matrix that corresponds to a code length and an information length according to the coded rate for every 72 columns in the column direction at a period of 72 columns, and
wherein the parity check matrix initial value table is formed as follows:
142 150 213 247 507 538 578 828 969 1042 1107 1315
1509 1584 1612 1781 1934 2106 2117
3 17 20 31 97 466 571 580 842 983 1152 1226 1261
1392 1413 1465 1480 2047 2125 49 169 258 548 582 839 873
881 931 995 1145 1209 1639 1654 1776 1826 1865 1906 1956
148 393 396 486 568 806 909 965 1203 1256 1306 1371
1402 1534 1664 1736 1844 1947 2055
185 191 263 290 384 769 981 1071 1202 1357 1554
1723 1769 1815 1842 1880 1910 1926 1991
424 444 923 1679
91 436 535 978
362 677 821 1695
1117 1392 1454 2030
35 840 1477 2152
1061 1202 1636 1879
242 286 1140 1538
111 240 481 760
59 1268 1899 2144
737 1299 1395 2072
34 288 810 1903
232 1013 1365 1729
410 783 1066 1187
113 885 1423 1560
760 909 1475 2048
68 254 420 1867
283 325 334 970
168 321 479 554
378 836 1913 1928
101 238 964 1393
304 460 1497 1588
151 192 1075 1614
297 313 677 1303
329 447 1348 1832
582 831 984 1900
2. A data processing device comprising:
an interchange means that interchanges code bits of mb bits in accordance with an allocation rule used for allocating the code bits of an LDPC code to symbol bits representing a symbol and sets code bits after interchange as the symbol bits in a case where the code bits of the LDPC (low density parity check) code having a code length of N bits are written in a column direction of a storage means storing the code bits in a row direction and the column direction, the m bits of the code bits of the LDPC code read in the row direction are set as one symbol, a predetermined positive integer is set as b, the storage means stores the mb bits in the row direction and stores N/(mb) bits in the column direction, the code bits of the LDPC code are written in the column direction of the storage means and then are read in the row direction, and the code bits of the mb bits read in the row direction of the storage means form b symbols,
wherein the LDPC code is an LDPC code having a code length N of 4,320 bits,
wherein the m bits are four bits, and the integer b is two,
wherein four bits of the code bits are mapped into one of 16 signal points that are determined in 16 QAM as one symbol,
wherein the storage means includes 8 columns storing 4×2 bits in the row direction and stores 4320/(4×2) bits in the column direction,
wherein the interchange means performs interchanging for allocation according to the allocation rule with the (#i+1)-th bit from the most significant bit of the code bits of 4×2 bits read in the row direction of the storage means being bit b#i and the (#i+1)-th bit from the most significant bit of the symbol bits of 4×2 bits of two consecutive symbols being bit y#i,
wherein the bit b 0 is allocated to the bit y 0 , the bit b 1 to the bit y 4 , the bit b 2 to the bit y 1 , the bit b 3 to the bit y 6 , the bit b 4 to the bit y 2 , the bit b 5 to the bit y 5 , the bit b 6 to the bit y 3 , the bit b 7 to the bit y 7 ,
wherein a coded rate of the LDPC code having a code length of 4,320 bits is 1/2,
wherein a parity check matrix of the LDPC code is configured by arranging elements of 1's of an information matrix that is determined by a parity check matrix initial value table representing positions of elements of 1's of the information matrix of the parity check matrix that corresponds to a code length and an information length according to the coded rate for every 72 columns in the column direction at a period of 72 columns, and
wherein the parity check matrix initial value table is formed as follows:
142 150 213 247 507 538 578 828 969 1042 1107 1315
1509 1584 1612 1781 1934 2106 2117
3 17 20 31 97 466 571 580 842 983 1152 1226 1261
1392 1413 1465 1480 2047 2125 49 169 258 548 582 839 873
881 931 995 1145 1209 1639 1654 1776 1826 1865 1906 1956
148 393 396 486 568 806 909 965 1203 1256 1306 1371
1402 1534 1664 1736 1844 1947 2055
185 191 263 290 384 769 981 1071 1202 1357 1554
1723 1769 1815 1842 1880 1910 1926 1991
424 444 923 1679
91 436 535 978
362 677 821 1695
1117 1392 1454 2030
35 840 1477 2152
1061 1202 1836 1879
242 286 1140 1538
111 240 481 760
59 1268 1899 2144
737 1299 1395 2072
34 288 810 1903
232 1013 1365 1729
410 783 1066 1187
113 885 1423 1560
760 909 1475 2048
68 254 420 1867
283 325 334 970
168 321 479 554
378 836 1913 1928
101 238 964 1393
304 460 1497 1588
151 192 1075 1614
297 313 677 1303
329 447 1348 1832
582 831 984 1900
3. A data processing device comprising:
an interchange means that interchanges code bits of mb bits in accordance with an allocation rule used for allocating the code bits of an LDPC code to symbol bits representing a symbol and sets code bits after interchange as the symbol bits in a case where the code bits of the LDPC (low density parity check) code having a code length of N bits are written in a column direction of a storage means storing the code bits in a row direction and the column direction, the m bits of the code bits of the LDPC code read in the row direction are set as one symbol, a predetermined positive integer is set as b, the storage means stores the mb bits in the row direction and stores N/(mb) bits in the column direction, the code bits of the LDPC code are written in the column direction of the storage means and then are read in the row direction, and the code bits of the mb bits read in the row direction of the storage means form b symbols,
wherein the LDPC code is an LDPC code having a code length N of 4,320 bits,
wherein the allocation rule is a rule that sets groups acquired by grouping the code bits of the mb bits in accordance with an error probability as code bit groups and groups acquired by grouping the symbol bits of the mb bits in accordance with an error probability as symbol bit groups and defines a group set that is a combination of the code bit group of the code bits and the symbol bit group of the symbol bits to which the code bits of the code bit group are allocated and the bit numbers of the code bits and the symbol bits of each one of the code bit group and the symbol bit group of the group set,
wherein, in a case where the m bits are four bits, the integer b is two, and four bits of the code bits are mapped into one of 16 signal points that are determined in 16 QAM as one symbol, the code bits of 4×2 bits are grouped into four code bit groups, and the symbol bits of 4×2 bits are grouped into two symbol bit groups,
wherein, in the allocation rule, allocation of one bit of the code bits of the code bit group of which the error probability is the best to one bit of the symbol bits of the symbol bit group of which the error probability is the best, allocation of two bits of the code bits of the code bit group of which the error probability is second best to two bits of the symbol bits of the symbol bit group of which the error probability is the best, allocation of one bit of the code bits of the code bit group of which the error probability is second best to one bit of the symbol bits of the symbol bit group of which the error probability is second best, allocation of one bit of the code bits of the code bit group of which the error probability is third best to one bit of the symbol bits of the symbol bit group of which the error probability is the best, and allocation of three bits of the code bits of the code bit group of which the error probability is fourth best to three bits of the symbol bits of the symbol bit group of which the error probability is second best are defined,
wherein a coded rate of the LDPC code having a code length of 4,320 bits is 7/12,
wherein a parity check matrix of the LDPC code is configured by arranging elements of 1's of an information matrix that is determined by a parity check matrix initial value table representing positions of elements of 1's of the information matrix of the parity check matrix that corresponds to a code length and an information length according to the coded rate for every 72 columns in the column direction at a period of 72 columns, and
wherein the parity check matrix initial value table is formed as follows:
96 246 326 621 668 748 874 965 1022 1108 1117 1142
1300 1469 1481 1627 1702
22 79 122 127 339 359 516 587 1025 1143 1294 1478
1484 1594 1651 1681 1794
80 426 429 506 599 810 892 1016 1117 1246 1277 1281
1316 1384 1713 1729 1753
15 145 182 305 451 563 570 635 781 827 983 1123
1204 1244 1311 1317 1348
11 157 164 292 301 360 636 859 871 895 1138 1164
1206 1268 1454 1613 1783
455 610 1123 1603
631 914 1424 1461
149 507 1275 1468
5 1078 1415 1735
169 772 775 1516
1207 1315 1683 1688
19 1053 1221 1260
933 1095 1597 1628
893 1209 1360 1740
1222 1486 1675 1737
897 1074 1651 1728
115 730 1363 1752
1552 1672 1734 1795
75 1087 1371 1712
123 438 839 1074
4 203 1407 1798
441 476 658 1400
380 1341 1741 1774
974 1487 1664 1756
7 273 834 1658
798 1475 1653 1686
12 1237 1539 1709
211 1494 1618 1624
367 1036 1390 1587
18 166 1645 1679
530 1092 1571 1707
588 1593 1689 1707
980 1104 1522 1701
1025 1510 1552 1683
270 340 1326 1770
4. A data processing device comprising:
an interchange means that interchanges code bits of mb bits in accordance with an allocation rule used for allocating the code bits of an LDPC code to symbol bits representing a symbol and sets code bits after interchange as the symbol bits in a case where the code bits of the LDPC (low density parity check) code having a code length of N bits are written in a column direction of a storage means storing the code bits in a row direction and the column direction, the m bits of the code bits of the LDPC code read in the row direction are set as one symbol, a predetermined positive integer is set as b, the storage means stores the mb bits in the row direction and stores N/(mb) bits in the column direction, the code bits of the LDPC code are written in the column direction of the storage means and then are read in the row direction, and the code bits of the mb bits read in the row direction of the storage means form b symbols,
wherein the LDPC code is an LDPC code having a code length N of 4,320 bits,
wherein the m bits are four bits, and the integer b is two,
wherein four bits of the code bits are mapped into one of 16 signal points that are determined in 16 QAM as one symbol,
wherein the storage means includes 8 columns storing 4×2 bits in the row direction and stores 4320/(4×2) bits in the column direction,
wherein the interchange means performs interchanging for allocation according to the allocation rule with the (#i+1)-th bit from the most significant bit of the code bits of 4×2 bits read in the row direction of the storage means being bit b#i and the (#i+1)-th bit from the most significant bit of the symbol bits of 4×2 bits of two consecutive symbols being bit y#i,
wherein the bit b 0 is allocated to the bit y 0 , the bit b 1 to the bit y 4 , the bit b 2 to the bit y 5 , the bit b 3 to the bit y 2 , the bit b 4 to the bit y 1 , the bit b 5 to the bit y 6 , the bit b 6 to the bit y 3 , and the bit b 7 to the bit y 7 ,
wherein a coded rate of the LDPC code having a code length of 4,320 bits is 7/12,
wherein a parity check matrix of the LDPC code is configured by arranging elements of 1's of an information matrix that is determined by a parity check matrix initial value table representing positions of elements of 1's of the information matrix of the parity check matrix that corresponds to a code length and an information length according to the coded rate for every 72 columns in the column direction at a period of 72 columns, and
wherein the parity check matrix initial value table is formed as follows:
96 246 326 621 668 748 874 965 1022 1108 1117 1142
1300 1469 1481 1627 1702
22 79 122 127 339 359 516 587 1025 1143 1294 1478
1484 1594 1651 1681 1794
80 426 429 506 599 810 892 1016 1117 1246 1277 1281
1316 1384 1713 1729 1753
15 145 182 305 451 563 570 635 781 827 983 1123
1204 1244 1311 1317 1348
11 157 164 292 301 360 636 859 871 895 1138 1164
1206 1268 1454 1613 1783
455 610 1123 1603
631 914 1424 1461
149 507 1275 1468
5 1078 1415 1735
169 772 775 1516
1207 1315 1683 1688
19 1053 1221 1260
933 1095 1597 1628
893 1209 1360 1740
1222 1486 1675 1737
897 1074 1651 1728
115 730 1363 1752
1552 1672 1734 1795
75 1087 1371 1712
123 438 839 1074
4 203 1407 1798
441 476 658 1400
380 1341 1741 1774
974 1487 1664 1756
7 273 834 1658
798 1475 1653 1686
12 1237 1539 1709
211 1494 1618 1624
367 1036 1390 1587
18 166 1645 1679
530 1092 1571 1707
588 1593 1689 1707
980 1104 1522 1701
1025 1510 1552 1683
270 340 1326 1770
5. A data processing device comprising:
an interchange means that interchanges code bits of mb bits in accordance with an allocation rule used for allocating the code bits of an LDPC code to symbol bits representing a symbol and sets code bits after interchange as the symbol bits in a case where the code bits of the LDPC (low density parity check) code having a code length of N bits are written in a column direction of a storage means storing the code bits in a row direction and the column direction, the m bits of the code bits of the LDPC code read in the row direction are set as one symbol, a predetermined positive integer is set as b, the storage means stores the mb bits in the row direction and stores N/(mb) bits in the column direction, the code bits of the LDPC code are written in the column direction of the storage means and then are read in the row direction, and the code bits of the mb bits read in the row direction of the storage means form b symbols,
wherein the LDPC code is an LDPC code having a code length N of 4,320 bits,
wherein the allocation rule is a rule that sets groups acquired by grouping the code bits of the mb bits in accordance with an error probability as code bit groups and groups acquired by grouping the symbol bits of the mb bits in accordance with an error probability as symbol bit groups and defines a group set that is a combination of the code bit group of the code bits and the symbol bit group of the symbol bits to which the code bits of the code bit group are allocated and the bit numbers of the code bits and the symbol bits of each one of the code bit group and the symbol bit group of the group set,
wherein, in a case where the m bits are four bits, the integer b is two, and four bits of the code bits are mapped into one of 16 signal points that are determined in 16 QAM as one symbol, the code bits of 4×2 bits are grouped into four code bit groups, and the symbol bits of 4×2 bits are grouped into two symbol bit groups,
wherein, in the allocation rule, allocation of one bit of the code bits of the code bit group of which the error probability is the best to one bit of the symbol bits of the symbol bit group of which the error probability is the best, allocation of three bits of the code bits of the code bit group of which the error probability is second best to three bits of the symbol bits of the symbol bit group of which the error probability is the best, allocation of one bit of the code bits of the code bit group of which the error probability is second best to one bit of the symbol bits of the symbol bit group of which the error probability is second best, allocation of one bit of the code bits of the code bit group of which the error probability is third best to one bit of the symbol bits of the symbol bit group of which the error probability is second best, and allocation of two bits of the code bits of the code bit group of which the error probability is fourth best to two bits of the symbol bits of the symbol bit group of which the error probability is second best are defined,
wherein a coded rate of the LDPC code having a code length of 4,320 bits is 2/3,
wherein a parity check matrix of the LDPC code is configured by arranging elements of 1's of an information matrix that is determined by a parity check matrix initial value table representing positions of elements of 1's of the information matrix of the parity check matrix that corresponds to a code length and an information length according to the coded rate for every 72 columns in the column direction at a period of 72 columns, and
wherein the parity check matrix initial value table is formed as follows:
56 291 315 374 378 665 682 713 740 884 923 927 1193
1203 1293 1372 1419 1428
1 17 113 402 406 504 559 597 686 697 817 878 983
1007 1034 1142 1231 1431
2 205 350 428 538 605 866 973 1008 1182 1252 1303
1319 1337 1346 1387 1417 1422
50 158 244 424 455 597 830 889 900 945 978 1040
1052 1059 1101 1150 1254 1382 41 53 269 316 449 604 704
752 937 952 1021 1031 1044 1068 1104 1265 1327 1348 601
911 1020 1260
151 674 732 1240
1099 1250 1348 1366
1115 1124 1394 1414
66 250 875 1040
525 603 916 1402
529 561 913 1089
1110 1243 1280 1372
137 656 1316 1369
5 458 1043 1381
1122 1171 1187 1335
18 130 312 1209
30 534 705 1294
272 727 955 1192
925 1287 1385 1437
11 446 1281 1408
614 716 787 1340
615 1147 1411 1416
284 865 1151 1414
202 689 1088 1144
459 633 838 941
46 301 1229 1367
476 1031 1120 1418
138 336 560 1419
168 357 536 938
1001 1052 1162 1414
349 1039 1353 1426
146 203 530 549
510 545 979 1108
479 1069 1106 1244
743 1019 1275 1348
427 721 1023 1435
73 842 1296 1435
323 1106 1140 1428
1074 1235 1353 1391
6. A data processing device comprising:
an interchange means that interchanges code bits of mb bits in accordance with an allocation rule used for allocating the code bits of an LDPC code to symbol bits representing a symbol and sets code bits after interchange as the symbol bits in a case where the code bits of the LDPC (low density parity check) code having a code length of N bits are written in a column direction of a storage means storing the code bits in a row direction and the column direction, the m bits of the code bits of the LDPC code read in the row direction are set as one symbol, a predetermined positive integer is set as b, the storage means stores the mb bits in the row direction and stores N/(mb) bits in the column direction, the code bits of the LDPC code are written in the column direction of the storage means and then are read in the row direction, and the code bits of the mb bits read in the row direction of the storage means form b symbols,
wherein the LDPC code is an LDPC code having a code length N of 4,320 bits,
wherein the m bits are four bits, and the integer b is two,
wherein four bits of the code bits are mapped into one of 16 signal points that are determined in 16 QAM as one symbol,
wherein the storage means includes 8 columns storing 4×2 bits in the row direction and stores 4320/(4×2) bits in the column direction,
wherein the interchange means performs interchanging for allocation according to the allocation rule with the (#i+1)-th bit from the most significant bit of the code bits of 4×2 bits read in the row direction of the storage means being bit b#i and the (#i+1)-th bit from the most significant bit of the symbol bits of 4×2 bits of two consecutive symbols being bit y#i,
wherein the bit b 0 is allocated to the bit y 0 , the bit b 1 to the bit y 4 , the bit b 2 to the bit y 5 , the bit b 3 to the bit y 2 , the bit b 4 to the bit y 1 , the bit b 5 to the bit y 6 , the bit b 6 to the bit y 3 , and the bit b 7 to the bit y 7 ,
wherein a coded rate of the LDPC code having a code length of 4,320 bits is 2/3,
wherein a parity check matrix of the LDPC code is configured by arranging elements of 1's of an information matrix that is determined by a parity check matrix initial value table representing positions of elements of 1's of the information matrix of the parity check matrix that corresponds to a code length and an information length according to the coded rate for every 72 columns in the column direction at a period of 72 columns, and
wherein the parity check matrix initial value table is formed as follows:
56 291 315 374 378 665 682 713 740 884 923 927 1193
1203 1293 1372 1419 1428
1 17 113 402 406 504 559 597 686 697 817 878 983
1007 1034 1142 1231 1431
2 205 350 428 538 605 866 973 1008 1182 1252 1303
1319 1337 1346 1387 1417 1422
50 158 244 424 455 597 830 889 900 945 978 1040
1052 1059 1101 1150 1254 1382 41 53 269 316 449 604 704
752 937 952 1021 1031 1044 1068 1104 1265 1327 1348 601
911 1020 1260
151 674 732 1240
1099 1250 1348 1366
1115 1124 1394 1414
66 250 875 1040
525 603 916 1402
529 561 913 1089
1110 1243 1280 1372
137 656 1316 1369
5 458 1043 1381
1122 1171 1187 1335
18 130 312 1209
30 534 705 1294
272 727 955 1192
925 1287 1385 1437
11 446 1281 1408
614 716 787 1340
615 1147 1411 1416
284 865 1151 1414
202 689 1088 1144
459 633 838 941
46 301 1229 1367
476 1031 1120 1418
138 336 560 1419
168 357 536 938
1001 1052 1162 1414
349 1039 1353 1426
146 203 530 549
510 545 979 1108
479 1069 1106 1244
743 1019 1275 1348
427 721 1023 1435
73 842 1296 1435
323 1106 1140 1428
1074 1235 1353 1391
7. A data processing device comprising:
an interchange means that interchanges code bits of mb bits in accordance with an allocation rule used for allocating the code bits of an LDPC code to symbol bits representing a symbol and sets code bits after interchange as the symbol bits in a case where the code bits of the LDPC (low density parity check) code having a code length of N bits are written in a column direction of a storage means storing the code bits in a row direction and the column direction, the m bits of the code bits of the LDPC code read in the row direction are set as one symbol, a predetermined positive integer is set as b, the storage means stores the mb bits in the row direction and stores N/(mb) bits in the column direction, the code bits of the LDPC code are written in the column direction of the storage means and then are read in the row direction, and the code bits of the mb bits read in the row direction of the storage means form b symbols,
wherein the LDPC code is an LDPC code having a code length N of 4,320 bits,
wherein the allocation rule is a rule that sets groups acquired by grouping the code bits of the mb bits in accordance with an error probability as code bit groups and groups acquired by grouping the symbol bits of the mb bits in accordance with an error probability as symbol bit groups and defines a group set that is a combination of the code bit group of the code bits and the symbol bit group of the symbol bits to which the code bits of the code bit group are allocated and the bit numbers of the code bits and the symbol bits of each one of the code bit group and the symbol bit group of the group set,
wherein, in a case where the m bits are four bits, the integer b is two, and four bits of the code bits are mapped into one of 16 signal points that are determined in 16 QAM as one symbol, the code bits of 4×2 bits are grouped into three code bit groups, and the symbol bits of 4×2 bits are grouped into two symbol bit groups,
wherein, in the allocation rule, allocation of one bit of the code bits of the code bit group of which the error probability is the best to one bit of the symbol bits of the symbol bit group of which the error probability is the best, allocation of three bits of the code bits of the code bit group of which the error probability is second best to three bits of the symbol bits of the symbol bit group of which the error probability is the best, allocation of two bits of the code bits of the code bit group of which the error probability is second best to two bits of the symbol bits of the symbol bit group of which the error probability is second best, and allocation of two bits of the code bits of the code bit group of which the error probability is third best to two bits of the symbol bits of the symbol bit group of which the error probability is second best are defined,
wherein a coded rate of the LDPC code having a code length of 4,320 bits is 3/4,
wherein a parity check matrix of the LDPC code is configured by arranging elements of 1's of an information matrix that is determined by a parity check matrix initial value table representing positions of elements of 1's of the information matrix of the parity check matrix that corresponds to a code length and an information length according to the coded rate for every 72 columns in the column direction at a period of 72 columns, and
wherein the parity check matrix initial value table is formed as follows:
3 14 207 304 349 414 577 587 748 761 772 855 920
976 1009 1058 1069
4 61 81 86 136 146 257 392 402 594 812 959 972 1037
1055 1064 1076
0 68 160 237 437 512 624 629 652 702 818 858 943
998 1035 1044 1064
10 42 159 215 254 320 373 382 410 492 630 887 889
911 916 975 1069
12 32 298 302 318 425 558 621 670 779 964 967 970
975 1054 1067 1072
124 381 715 981
503 610 633 1030
321 874 900 1020
509 817 902 978
3 118 688 911
515 644 848 1067
13 75 721 970
9 464 756 1023
26 219 304 672
5 310 410 695
0 7 267 1040
76 822 873 1043
7 129 1010 1065
115 156 714 1003
163 480 505 1079
238 601 743 1046
216 702 738 912
13 20 166 979
11 14 261 1051
186 476 595 843
13 237 451 532
7 11 594 738
10 225 495 851
520 675 1018 1045
9 352 514 543
60 917 1071 1074
471 556 673 1062
345 350 1043 1076
5 539 788 1061
704 851 883 1049
211 233 242 1072
9 1047 1057 1076
18 172 473 1042
365 488 921 968
211 216 554 824
1 709 923 1074
576 647 901 963
71 676 1053 1073
265 738 958 969
66 274 774 811
8. A data processing device comprising:
an interchange means that interchanges code bits of mb bits in accordance with an allocation rule used for allocating the code bits of an LDPC code to symbol bits representing a symbol and sets code bits after interchange as the symbol bits in a case where the code bits of the LDPC (low density parity check) code having a code length of N bits are written in a column direction of a storage means storing the code bits in a row direction and the column direction, the m bits of the code bits of the LDPC code read in the row direction are set as one symbol, a predetermined positive integer is set as b, the storage means stores the mb bits in the row direction and stores N/(mb) bits in the column direction, the code bits of the LDPC code are written in the column direction of the storage means and then are read in the row direction, and the code bits of the mb bits read in the row direction of the storage means form b symbols,
wherein the LDPC code is an LDPC code having a code length N of 4,320 bits,
wherein the m bits are four bits, and the integer b is two,
wherein four bits of the code bits are mapped into one of 16 signal points that are determined in 16 QAM as one symbol,
wherein the storage means includes 8 columns storing 4×2 bits in the row direction and stores 4320/(4×2) bits in the column direction,
wherein the interchange means performs interchanging for allocation according to the allocation rule with the (#i+1)-th bit from the most significant bit of the code bits of 4×2 bits read in the row direction of the storage means being bit b#i and the (#i+1)-th bit from the most significant bit of the symbol bits of 4×2 bits of two consecutive symbols being bit y#i,
wherein the bit b 0 is allocated to the bit y 0 , the bit b 1 to the bit y 4 , the bit b 2 to the bit y 5 , the bit b 3 to the bit y 2 , the bit b 4 to the bit y 1 , the bit b 5 to the bit y 6 , the bit b 6 to the bit y 3 , and the bit b 7 to the bit y 7 ,
wherein a coded rate of the LDPC code having a code length of 4,320 bits is 3/4,
wherein a parity check matrix of the LDPC code is configured by arranging elements of 1's of an information matrix that is determined by a parity check matrix initial value table representing positions of elements of 1's of the information matrix of the parity check matrix that corresponds to a code length and an information length according to the coded rate for every 72 columns in the column direction at a period of 72 columns, and
wherein the parity check matrix initial value table is formed as follows:
3 14 207 304 349 414 577 587 748 761 772 855 920
976 1009 1058 1069
4 61 81 86 136 146 257 392 402 594 812 959 972 1037
1055 1064 1076
0 68 160 237 437 512 624 629 652 702 818 858 943
998 1035 1044 1064
10 42 159 215 254 320 373 382 410 492 630 887 889
911 916 975 1069
12 32 298 302 318 425 558 621 670 779 964 967 970
975 1054 1067 1072 124 381 715 981
503 610 633 1030
321 874 900 1020
509 817 902 978
3 118 688 911
515 644 848 1067
13 75 721 970
9 464 756 1023
26 219 304 672
5 310 410 695
0 7 267 1040
76 822 873 1043
7 129 1010 1065
115 156 714 1003
163 480 505 1079
238 601 743 1046
216 702 738 912
13 20 166 979
11 14 261 1051
186 476 595 843
13 237 451 532
7 11 594 738
10 225 495 851
520 675 1018 1045
9 352 514 543
60 917 1071 1074
471 556 673 1062
345 350 1043 1076
5 539 788 1061 704 851 883 1049
211 233 242 1072
9 1047 1057 1076
18 172 473 1042
365 488 921 968
211 216 554 824
1 709 923 1074
576 647 901 963
71 676 1053 1073
265 738 958 969
66 274 774 811
9. A data processing method comprising:
interchanging code bits of mb bits in accordance with an allocation rule used for allocating the code bits of an LDPC code to symbol bits representing a symbol and sets code bits after interchange as the symbol bits in a case where the code bits of the LDPC (low density parity check) code having a code length of N bits are written in a column direction of a storage means storing the code bits in a row direction and the column direction, the m bits of the code bits of the LDPC code read in the row direction are set as one symbol, a predetermined positive integer is set as b, the storage means stores the mb bits in the row direction and stores N/(mb) bits in the column direction, the code bits of the LDPC code are written in the column direction of the storage means and then are read in the row direction, and the code bits of the mb bits read in the row direction of the storage means form b symbols,
wherein the LDPC code is an LDPC code having a code length N of 4,320 bits,
wherein the allocation rule is a rule that sets groups acquired by grouping the code bits of the mb bits in accordance with an error probability as code bit groups and groups acquired by grouping the symbol bits of the mb bits in accordance with an error probability as symbol bit groups and defines a group set that is a combination of the code bit group of the code bits and the symbol bit group of the symbol bits to which the code bits of the code bit group are allocated and the bit numbers of the code bits and the symbol bits of each one of the code bit group and the symbol bit group of the group set,
wherein, in a case where the m bits are four bits, the integer b is two, and four bits of the code bits are mapped into one of 16 signal points that are determined in 16 QAM as one symbol, the code bits of 4×2 bits are grouped into three code bit groups, and the symbol bits of 4×2 bits are grouped into two symbol bit groups,
wherein, in the allocation rule, allocation of one bit of the code bits of the code bit group of which the error probability is the best to one bit of the symbol bits of the symbol bit group of which the error probability is the best, allocation of two bits of the code bits of the code bit group of which the error probability is second best to two bits of the symbol bits of the symbol bit group of which the error probability is the best, allocation of one bit of the code bits of the code bit group of which the error probability is second best to one bit of the symbol bits of the symbol bit group of which the error probability is second best, allocation of one bit of the code bits of the code bit group of which the error probability is third best to one bit of the symbol bits of the symbol bit group of which the error probability is the best, and allocation of three bits of the code bits of the code bit group of which the error probability is third best to three bits of the symbol bits of the symbol bit group of which the error probability is second best are defined,
wherein a coded rate of the LDPC code having a code length of 4,320 bits is 1/2,
wherein a parity check matrix of the LDPC code is configured by arranging elements of 1's of an information matrix that is determined by a parity check matrix initial value table representing positions of elements of 1's of the information matrix of the parity check matrix that corresponds to a code length and an information length according to the coded rate for every 72 columns in the column direction at a period of 72 columns, and
wherein the parity check matrix initial value table is formed as follows:
142 150 213 247 507 538 578 828 969 1042 1107 1315
1509 1584 1612 1781 1934 2106 2117
3 17 20 31 97 466 571 580 842 983 1152 1226 1261
1392 1413 1465 1480 2047 2125 49 169 258 548 582 839 873
881 931 995 1145 1209 1639 1654 1776 1826 1865 1906 1956
148 393 396 486 568 806 909 965 1203 1256 1306 1371
1402 1534 1664 1736 1844 1947 2055
185 191 263 290 384 769 981 1071 1202 1357 1554
1723 1769 1815 1842 1880 1910 1926 1991
424 444 923 1679
91 436 535 978
362 677 821 1695
1117 1392 1454 2030
35 840 1477 2152
1061 1202 1836 1879
242 286 1140 1538
111 240 481 760
59 1268 1899 2144
737 1299 1395 2072
34 288 810 1903
232 1013 1365 1729
410 783 1066 1187
113 885 1423 1560
760 909 1475 2048
68 254 420 1867
283 325 334 970
168 321 479 554
378 836 1913 1928
101 238 964 1393
304 460 1497 1588
151 192 1075 1614
297 313 677 1303
329 447 1348 1832
582 831 984 1900
10. A data processing method comprising:
interchanging code bits of mb bits in accordance with an allocation rule used for allocating the code bits of an LDPC code to symbol bits representing a symbol and sets code bits after interchange as the symbol bits in a case where the code bits of the LDPC (low density parity check) code having a code length of N bits are written in a column direction of a storage means storing the code bits in a row direction and the column direction, the m bits of the code bits of the LDPC code read in the row direction are set as one symbol, a predetermined positive integer is set as b, the storage means stores the mb bits in the row direction and stores N/(mb) bits in the column direction, the code bits of the LDPC code are written in the column direction of the storage means and then are read in the row direction, and the code bits of the mb bits read in the row direction of the storage means form b symbols,
wherein the LDPC code is an LDPC code having a code length N of 4,320 bits,
wherein the m bits are four bits, and the integer b is two,
wherein four bits of the code bits are mapped into one of 16 signal points that are determined in 16 QAM as one symbol,
wherein the storage means includes 8 columns storing 4×2 bits in the row direction and stores 4320/(4×2) bits in the column direction,
wherein, in the interchanging of code bits, interchanging for allocation according to the allocation rule is performed with the (#i+1)-th bit from the most significant bit of the code bits of 4×2 bits read in the row direction of the storage means being bit b#i and the (#i+1)-th bit from the most significant bit of the symbol bits of 4×2 bits of two consecutive symbols being bit y#i,
wherein the bit b 0 is allocated to the bit y 0 , the bit b 1 to the bit y 4 , the bit b 2 to the bit y 1 , the bit b 3 to the bit y 6 , the bit b 4 to the bit y 2 , the bit b 5 to the bit y 5 , the bit b 6 to the bit y 3 , and the bit b 7 to the bit y 7 ,
wherein a coded rate of the LDPC code having a code length of 4,320 bits is 1/2,
wherein a parity check matrix of the LDPC code is configured by arranging elements of 1's of an information matrix that is determined by a parity check matrix initial value table representing positions of elements of 1's of the information matrix of the parity check matrix that corresponds to a code length and an information length according to the coded rate for every 72 columns in the column direction at a period of 72 columns, and
wherein the parity check matrix initial value table is formed as follows:
142 150 213 247 507 538 578 828 969 1042 1107 1315
1509 1584 1612 1781 1934 2106 2117
3 17 20 31 97 466 571 580 842 983 1152 1226 1261
1392 1413 1465 1480 2047 2125 49 169 258 548 582 839 873
881 931 995 1145 1209 1639 1654 1776 1826 1865 1906 1956
148 393 396 486 568 806 909 965 1203 1256 1306 1371
1402 1534 1664 1736 1844 1947 2055
185 191 263 290 384 769 981 1071 1202 1357 1554
1723 1769 1815 1842 1880 1910 1926 1991
424 444 923 1679
91 436 535 978
362 677 821 1695
1117 1392 1454 2030
35 840 1477 2152
1061 1202 1836 1879
242 286 1140 1538
111 240 481 760
59 1268 1899 2144
737 1299 1395 2072
34 288 810 1903
232 1013 1365 1729
410 783 1066 1187
113 885 1423 1560
760 909 1475 2048
68 254 420 1867
283 325 334 970
168 321 479 554
378 836 1913 1928
101 238 964 1393
304 460 1497 1588
151 192 1075 1614
297 313 677 1303
329 447 1348 1832
582 831 984 1900
11. A data processing method comprising:
interchanging code bits of mb bits in accordance with an allocation rule used for allocating the code bits of an LDPC code to symbol bits representing a symbol and sets code bits after interchange as the symbol bits in a case where the code bits of the LDPC (low density parity check) code having a code length of N bits are written in a column direction of a storage means storing the code bits in a row direction and the column direction, the m bits of the code bits of the LDPC code read in the row direction are set as one symbol, a predetermined positive integer is set as b, the storage means stores the mb bits in the row direction and stores N/(mb) bits in the column direction, the code bits of the LDPC code are written in the column direction of the storage means and then are read in the row direction, and the code bits of the mb bits read in the row direction of the storage means form b symbols,
wherein the LDPC code is an LDPC code having a code length N of 4,320 bits,
wherein the allocation rule is a rule that sets groups acquired by grouping the code bits of the mb bits in accordance with an error probability as code bit groups and groups acquired by grouping the symbol bits of the mb bits in accordance with an error probability as symbol bit groups and defines a group set that is a combination of the code bit group of the code bits and the symbol bit group of the symbol bits to which the code bits of the code bit group are allocated and the bit numbers of the code bits and the symbol bits of each one of the code bit group and the symbol bit group of the group set,
wherein, in a case where the m bits are four bits, the integer b is two, and four bits of the code bits are mapped into one of 16 signal points that are determined in 16 QAM as one symbol, the code bits of 4×2 bits are grouped into four code bit groups, and the symbol bits of 4×2 bits are grouped into two symbol bit groups,
wherein, in the allocation rule, allocation of one bit of the code bits of the code bit group of which the error probability is the best to one bit of the symbol bits of the symbol bit group of which the error probability is the best, allocation of two bits of the code bits of the code bit group of which the error probability is second best to two bits of the symbol bits of the symbol bit group of which the error probability is the best, allocation of one bit of the code bits of the code bit group of which the error probability is second best to one bit of the symbol bits of the symbol bit group of which the error probability is second best, allocation of one bit of the code bits of the code bit group of which the error probability is third best to one bit of the symbol bits of the symbol bit group of which the error probability is the best, and allocation of three bits of the code bits of the code bit group of which the error probability is fourth best to three bits of the symbol bits of the symbol bit group of which the error probability is second best are defined,
wherein a coded rate of the LDPC code having a code length of 4,320 bits is 7/12,
wherein a parity check matrix of the LDPC code is configured by arranging elements of 1's of an information matrix that is determined by a parity check matrix initial value table representing positions of elements of 1's of the information matrix of the parity check matrix that corresponds to a code length and an information length according to the coded rate for every 72 columns in the column direction at a period of 72 columns, and
wherein the parity check matrix initial value table is formed as follows:
96 246 326 621 668 748 874 965 1022 1108 1117 1142
1300 1469 1481 1627 1702
22 79 122 127 339 359 516 587 1025 1143 1294 1478
1484 1594 1651 1681 1794
80 426 429 506 599 810 892 1016 1117 1246 1277 1281
1316 1384 1713 1729 1753
15 145 182 305 451 563 570 635 781 827 983 1123
1204 1244 1311 1317 1348
11 157 164 292 301 360 636 859 871 895 1138 1164
1206 1268 1454 1613 1783
455 610 1123 1603
631 914 1424 1461
149 507 1275 1468
5 1078 1415 1735
169 772 775 1516
1207 1315 1683 1688
19 1053 1221 1260
933 1095 1597 1628
893 1209 1360 1740
1222 1486 1675 1737
897 1074 1651 1728
115 730 1363 1752
1552 1672 1734 1795
75 1087 1371 1712
123 438 839 1074
4 203 1407 1798
441 476 658 1400
380 1341 1741 1774
974 1487 1664 1756
7 273 834 1658
798 1475 1653 1686
12 1237 1539 1709
211 1494 1618 1624
367 1036 1390 1587
18 166 1645 1679
530 1092 1571 1707
588 1593 1689 1707
980 1104 1522 1701
1025 1510 1552 1683
270 340 1326 1770
12. A data processing method comprising:
interchanging code bits of mb bits in accordance with an allocation rule used for allocating the code bits of an LDPC code to symbol bits representing a symbol and sets code bits after interchange as the symbol bits in a case where the code bits of the LDPC (low density parity check) code having a code length of N bits are written in a column direction of a storage means storing the code bits in a row direction and the column direction, the m bits of the code bits of the LDPC code read in the row direction are set as one symbol, a predetermined positive integer is set as b, the storage means stores the mb bits in the row direction and stores N/(mb) bits in the column direction, the code bits of the LDPC code are written in the column direction of the storage means and then are read in the row direction, and the code bits of the mb bits read in the row direction of the storage means form b symbols,
wherein the LDPC code is an LDPC code having a code length N of 4,320 bits,
wherein the m bits are four bits, and the integer b is two,
wherein four bits of the code bits are mapped into one of 16 signal points that are determined in 16 QAM as one symbol,
wherein the storage means includes 8 columns storing 4×2 bits in the row direction and stores 4320/(4×2) bits in the column direction,
wherein, in the interchanging of code bits, interchanging for allocation according to the allocation rule is performed with the (#i+1)-th bit from the most significant bit of the code bits of 4×2 bits read in the row direction of the storage means being bit b#i and the (#i+1)-th bit from the most significant bit of the symbol bits of 4×2 bits of two consecutive symbols being bit y#i,
wherein the bit b 0 is allocated to the bit y 0 , the bit b 1 to the bit y 4 , the bit b 2 to the bit y 5 , the bit b 3 to the bit y 2 , the bit b 4 to the bit y 1 , the bit b 5 to the bit y 6 , the bit b 6 to the bit y 3 , and the bit b 7 to the bit y 7 ,
wherein a coded rate of the LDPC code having a code length of 4,320 bits is 7/12,
wherein a parity check matrix of the LDPC code is configured by arranging elements of 1's of an information matrix that is determined by a parity check matrix initial value table representing positions of elements of 1's of the information matrix of the parity check matrix that corresponds to a code length and an information length according to the coded rate for every 72 columns in the column direction at a period of 72 columns, and
wherein the parity check matrix initial value table is formed as follows:
96 246 326 621 668 748 874 965 1022 1108 1117 1142
1300 1469 1481 1627 1702
22 79 122 127 339 359 516 587 1025 1143 1294 1478
1484 1594 1651 1681 1794
80 426 429 506 599 810 892 1016 1117 1246 1277 1281
1316 1384 1713 1729 1753
15 145 182 305 451 563 570 635 781 827 983 1123
1204 1244 1311 1317 1348
11 157 164 292 301 360 636 859 871 895 1138 1164
1206 1268 1454 1613 1783
455 610 1123 1603
631 914 1424 1461
149 507 1275 1468
5 1078 1415 1735
169 772 775 1516
1207 1315 1683 1688
19 1053 1221 1260
933 1095 1597 1628
893 1209 1360 1740
1222 1486 1675 1737
897 1074 1651 1728
115 730 1363 1752
1552 1672 1734 1795
75 1087 1371 1712
123 438 839 1074
4 203 1407 1798
441 476 658 1400
380 1341 1741 1774
974 1487 1664 1756
7 273 834 1658
798 1475 1653 1686
12 1237 1539 1709
211 1494 1618 1624
367 1036 1390 1587
18 166 1645 1679
530 1092 1571 1707
588 1593 1689 1707
980 1104 1522 1701
1025 1510 1552 1683
270 340 1326 1770
13. A data processing method comprising:
interchanging code bits of mb bits in accordance with an allocation rule used for allocating the code bits of an LDPC code to symbol bits representing a symbol and sets code bits after interchange as the symbol bits in a case where the code bits of the LDPC (low density parity check) code having a code length of N bits are written in a column direction of a storage means storing the code bits in a row direction and the column direction, the m bits of the code bits of the LDPC code read in the row direction are set as one symbol, a predetermined positive integer is set as b, the storage means stores the mb bits in the row direction and stores N/(mb) bits in the column direction, the code bits of the LDPC code are written in the column direction of the storage means and then are read in the row direction, and the code bits of the mb bits read in the row direction of the storage means form b symbols,
wherein the LDPC code is an LDPC code having a code length N of 4,320 bits,
wherein the allocation rule is a rule that sets groups acquired by grouping the code bits of the mb bits in accordance with an error probability as code bit groups and groups acquired by grouping the symbol bits of the mb bits in accordance with an error probability as symbol bit groups and defines a group set that is a combination of the code bit group of the code bits and the symbol bit group of the symbol bits to which the code bits of the code bit group are allocated and the bit numbers of the code bits and the symbol bits of each one of the code bit group and the symbol bit group of the group set,
wherein, in a case where the m bits are four bits, the integer b is two, and four bits of the code bits are mapped into one of 16 signal points that are determined in 16 QAM as one symbol, the code bits of 4×2 bits are grouped into four code bit groups, and the symbol bits of 4×2 bits are grouped into two symbol bit groups,
wherein, in the allocation rule, allocation of one bit of the code bits of the code bit group of which the error probability is the best to one bit of the symbol bits of the symbol bit group of which the error probability is the best, allocation of three bits of the code bits of the code bit group of which the error probability is second best to three bits of the symbol bits of the symbol bit group of which the error probability is the best, allocation of one bit of the code bits of the code bit group of which the error probability is second best to one bit of the symbol bits of the symbol bit group of which the error probability is second best, allocation of one bit of the code bits of the code bit group of which the error probability is third best to one bit of the symbol bits of the symbol bit group of which the error probability is second best, and allocation of two bits of the code bits of the code bit group of which the error probability is fourth best to two bits of the symbol bits of the symbol bit group of which the error probability is second best are defined,
wherein a coded rate of the LDPC code having a code length of 4,320 bits is 2/3,
wherein a parity check matrix of the LDPC code is configured by arranging elements of 1's of an information matrix that is determined by a parity check matrix initial value table representing positions of elements of 1's of the information matrix of the parity check matrix that corresponds to a code length and an information length according to the coded rate for every 72 columns in the column direction at a period of 72 columns, and
wherein the parity check matrix initial value table is formed as follows:
56 291 315 374 378 665 682 713 740 884 923 927 1193
1203 1293 1372 1419 1428
1 17 113 402 406 504 559 597 686 697 817 878 983
1007 1034 1142 1231 1431
2 205 350 428 538 605 866 973 1008 1182 1252 1303
1319 1337 1346 1387 1417 1422
50 158 244 424 455 597 830 889 900 945 978 1040
1052 1059 1101 1150 1254 1382 41 53 269 316 449 604 704
752 937 952 1021 1031 1044 1068 1104 1265 1327 1348 601
911 1020 1260
151 674 732 1240
1099 1250 1348 1366
1115 1124 1394 1414
66 250 875 1040
525 603 916 1402
529 561 913 1089
1110 1243 1280 1372
137 656 1316 1369
5 458 1043 1381
1122 1171 1187 1335
18 130 312 1209
30 534 705 1294
272 727 955 1192
925 1287 1385 1437
11 446 1281 1408
614 716 787 1340
615 1147 1411 1416
284 865 1151 1414
202 689 1088 1144
459 633 838 941
46 301 1229 1367
476 1031 1120 1418
138 336 560 1419
168 357 536 938
1001 1052 1162 1414
349 1039 1353 1426
146 203 530 549
510 545 979 1108
479 1069 1106 1244
743 1019 1275 1348
427 721 1023 1435
73 842 1296 1435
323 1106 1140 1428
1074 1235 1353 1391
14. A data processing method comprising:
interchanging code bits of mb bits in accordance with an allocation rule used for allocating the code bits of an LDPC code to symbol bits representing a symbol and sets code bits after interchange as the symbol bits in a case where the code bits of the LDPC (low density parity check) code having a code length of N bits are written in a column direction of a storage means storing the code bits in a row direction and the column direction, the m bits of the code bits of the LDPC code read in the row direction are set as one symbol, a predetermined positive integer is set as b, the storage means stores the mb bits in the row direction and stores N/(mb) bits in the column direction, the code bits of the LDPC code are written in the column direction of the storage means and then are read in the row direction, and the code bits of the mb bits read in the row direction of the storage means form b symbols,
wherein the LDPC code is an LDPC code having a code length N of 4,320 bits,
wherein the m bits are four bits, and the integer b is two,
wherein four bits of the code bits are mapped into one of 16 signal points that are determined in 16 QAM as one symbol,
wherein the storage means includes 8 columns storing 4×2 bits in the row direction and stores 4320/(4×2) bits in the column direction,
wherein, in the interchanging of code bits, interchanging for allocation according to the allocation rule is performed with the (#i+1)-th bit from the most significant bit of the code bits of 4×2 bits read in the row direction of the storage means being bit b#i and the (#i+1)-th bit from the most significant bit of the symbol bits of 4×2 bits of two consecutive symbols being bit y#i,
wherein the bit b 0 is allocated to the bit y 0 , the bit b 1 to the bit y 4 , the bit b 2 to the bit y 5 , the bit b 3 to the bit y 2 , the bit b 4 to the bit y 1 , the bit b 5 to the bit y 6 , the bit b 6 to the bit y 3 , and the bit b 7 to the bit y 7 ,
wherein a coded rate of the LDPC code having a code length of 4,320 bits is 2/3,
wherein a parity check matrix of the LDPC code is configured by arranging elements of 1's of an information matrix that is determined by a parity check matrix initial value table representing positions of elements of 1's of the information matrix of the parity check matrix that corresponds to a code length and an information length according to the coded rate for every 72 columns in the column direction at a period of 72 columns, and
wherein the parity check matrix initial value table is formed as follows:
56 291 315 374 378 665 682 713 740 884 923 927 1193
1203 1293 1372 1419 1428
1 17 113 402 406 504 559 597 686 697 817 878 983
1007 1034 1142 1231 1431
2 205 350 428 538 605 866 973 1008 1182 1252 1303
1319 1337 1346 1387 1417 1422
50 158 244 424 455 597 830 889 900 945 978 1040
1052 1059 1101 1150 1254 1382 41 53 269 316 449 604 704
752 937 952 1021 1031 1044 1068 1104 1265 1327 1348 601
911 1020 1260
151 674 732 1240
1099 1250 1348 1366
1115 1124 1394 1414
66 250 875 1040
525 603 916 1402
529 561 913 1089
1110 1243 1280 1372
137 656 1316 1369
5 458 1043 1381
1122 1171 1187 1335
18 130 312 1209
30 534 705 1294
272 727 955 1192
925 1287 1385 1437
11 446 1281 1408
614 716 787 1340
615 1147 1411 1416
284 865 1151 1414
202 689 1088 1144
459 633 838 941
46 301 1229 1367
476 1031 1120 1418
138 336 560 1419
168 357 536 938
1001 1052 1162 1414
349 1039 1353 1426
146 203 530 549
510 545 979 1108
479 1069 1106 1244
743 1019 1275 1348
427 721 1023 1435
73 842 1296 1435
323 1106 1140 1428
1074 1235 1353 1391
15. A data processing method comprising:
interchanging code bits of mb bits in accordance with an allocation rule used for allocating the code bits of an LDPC code to symbol bits representing a symbol and sets code bits after interchange as the symbol bits in a case where the code bits of the LDPC (low density parity check) code having a code length of N bits are written in a column direction of a storage means storing the code bits in a row direction and the column direction, the m bits of the code bits of the LDPC code read in the row direction are set as one symbol, a predetermined positive integer is set as b, the storage means stores the mb bits in the row direction and stores N/(mb) bits in the column direction, the code bits of the LDPC code are written in the column direction of the storage means and then are read in the row direction, and the code bits of the mb bits read in the row direction of the storage means form b symbols,
wherein the LDPC code is an LDPC code having a code length N of 4,320 bits,
wherein the allocation rule is a rule that sets groups acquired by grouping the code bits of the mb bits in accordance with an error probability as code bit groups and groups acquired by grouping the symbol bits of the mb bits in accordance with an error probability as symbol bit groups and defines a group set that is a combination of the code bit group of the code bits and the symbol bit group of the symbol bits to which the code bits of the code bit group are allocated and the bit numbers of the code bits and the symbol bits of each one of the code bit group and the symbol bit group of the group set,
wherein, in a case where the m bits are four bits, the integer b is two, and four bits of the code bits are mapped into one of 16 signal points that are determined in 16 QAM as one symbol, the code bits of 4×2 bits are grouped into three code bit groups, and the symbol bits of 4×2 bits are grouped into two symbol bit groups,
wherein, in the allocation rule, allocation of one bit of the code bits of the code bit group of which the error probability is the best to one bit of the symbol bits of the symbol bit group of which the error probability is the best, allocation of three bits of the code bits of the code bit group of which the error probability is second best to three bits of the symbol bits of the symbol bit group of which the error probability is the best, allocation of two bits of the code bits of the code bit group of which the error probability is second best to two bits of the symbol bits of the symbol bit group of which the error probability is second best, and allocation of two bits of the code bits of the code bit group of which the error probability is third best to two bits of the symbol bits of the symbol bit group of which the error probability is second best are defined,
wherein a coded rate of the LDPC code having a code length of 4,320 bits is 3/4,
wherein a parity check matrix of the LDPC code is configured by arranging elements of 1's of an information matrix that is determined by a parity check matrix initial value table representing positions of elements of 1's of the information matrix of the parity check matrix that corresponds to a code length and an information length according to the coded rate for every 72 columns in the column direction at a period of 72 columns, and
wherein the parity check matrix initial value table is formed as follows:
3 14 207 304 349 414 577 587 748 761 772 855 920
976 1009 1058 1069
4 61 81 86 136 146 257 392 402 594 812 959 972 1037
1055 1064 1076
0 68 160 237 437 512 624 629 652 702 818 858 943
998 1035 1044 1064
10 42 159 215 254 320 373 382 410 492 630 887 889
911 916 975 1069
12 32 298 302 318 425 558 621 670 779 964 967 970
975 1054 1067 1072
124 381 715 981
503 610 633 1030
321 874 900 1020
509 817 902 978
3 118 688 911
515 644 848 1067
13 75 721 970
9 464 756 1023
26 219 304 672
5 310 410 695
0 7 267 1040
76 822 873 1043
7 129 1010 1065
115 156 714 1003
163 480 505 1079
238 601 743 1046
216 702 738 912
13 20 166 979
11 14 261 1051
186 476 595 843
13 237 451 532
7 11 594 738
10 225 495 851
520 675 1018 1045
9 352 514 543
60 917 1071 1074
471 556 673 1062
345 350 1043 1076
5 539 788 1061
704 851 883 1049
211 233 242 1072
9 1047 1057 1076
18 172 473 1042
365 488 921 968
211 216 554 824
1 709 923 1074
576 647 901 963
71 676 1053 1073
265 738 958 969
66 274 774 811
16. A data processing method comprising:
interchanging code bits of mb bits in accordance with an allocation rule used for allocating the code bits of an LDPC code to symbol bits representing a symbol and sets code bits after interchange as the symbol bits in a case where the code bits of the LDPC (low density parity check) code having a code length of N bits are written in a column direction of a storage means storing the code bits in a row direction and the column direction, the m bits of the code bits of the LDPC code read in the row direction are set as one symbol, a predetermined positive integer is set as b, the storage means stores the mb bits in the row direction and stores N/(mb) bits in the column direction, the code bits of the LDPC code are written in the column direction of the storage means and then are read in the row direction, and the code bits of the mb bits read in the row direction of the storage means form b symbols,
wherein the LDPC code is an LDPC code having a code length N of 4,320 bits,
wherein the m bits are four bits, and the integer b is two,
wherein four bits of the code bits are mapped into one of 16 signal points that are determined in 16 QAM as one symbol,
wherein the storage means includes 8 columns storing 4×2 bits in the row direction and stores 4320/(4×2) bits in the column direction,
wherein, in the interchanging of code bits, interchanging for allocation according to the allocation rule is performed with the (#i+1)-th bit from the most significant bit of the code bits of 4×2 bits read in the row direction of the storage means being bit b#i and the (#i+1)-th bit from the most significant bit of the symbol bits of 4×2 bits of two consecutive symbols being bit y#i,
wherein the bit b 0 is allocated to the bit y 0 , the bit b 1 to the bit y 4 , the bit b 2 to the bit y 5 , the bit b 3 to the bit y 2 , the bit b 4 to the bit y 1 , the bit b 5 to the bit y 6 , the bit b 6 to the bit y 3 , and the bit b 7 to the bit y 7 ,
wherein a coded rate of the LDPC code having a code length of 4,320 bits is 3/4,
wherein a parity check matrix of the LDPC code is configured by arranging elements of 1's of an information matrix that is determined by a parity check matrix initial value table representing positions of elements of 1's of the information matrix of the parity check matrix that corresponds to a code length and an information length according to the coded rate for every 72 columns in the column direction at a period of 72 columns, and
wherein the parity check matrix initial value table is formed as follows:
3 14 207 304 349 414 577 587 748 761 772 855 920
976 1009 1058 1069
4 61 81 86 136 146 257 392 402 594 812 959 972 1037
1055 1064 1076
0 68 160 237 437 512 624 629 652 702 818 858 943
998 1035 1044 1064
10 42 159 215 254 320 373 382 410 492 630 887 889
911 916 975 1069
12 32 298 302 318 425 558 621 670 779 964 967 970
975 1054 1067 1072
124 381 715 981
503 610 633 1030
321 874 900 1020
509 817 902 978
3 118 688 911
515 644 848 1067
13 75 721 970
9 464 756 1023
26 219 304 672
5 310 410 695
0 7 267 1040
76 822 873 1043
7 129 1010 1065
115 156 714 1003
163 480 505 1079
238 601 743 1046
216 702 738 912
13 20 166 979
11 14 261 1051
186 476 595 843
13 237 451 532
7 11 594 738
10 225 495 851
520 675 1018 1045
9 352 514 543
60 917 1071 1074
471 556 673 1062
345 350 1043 1076
5 539 788 1061
704 851 883 1049
211 233 242 1072
9 1047 1057 1076
18 172 473 1042
365 488 921 968
211 216 554 824
1 709 923 1074
576 647 901 963
71 676 1053 1073
265 738 958 969
66 274 774 811
17. A data processing device comprising:
an interchange means that interchanges code bits of mb bits in accordance with an allocation rule used for allocating the code bits of an LDPC code to symbol bits representing a symbol and sets code bits after interchange as the symbol bits in a case where the code bits of the LDPC (low density parity check) code having a code length of N bits are written in a column direction of a storage means storing the code bits in a row direction and the column direction, the m bits of the code bits of the LDPC code read in the row direction are set as one symbol, a predetermined positive integer is set as b, the storage means stores the mb bits in the row direction and stores N/(mb) bits in the column direction, the code bits of the LDPC code are written in the column direction of the storage means and then are read in the row direction, and the code bits of the mb bits read in the row direction of the storage means form b symbols; and
a reverse interchanging means that performs a reverse interchanging process in which the positions of the code bits after interchange, which are acquired from a transmission device, are returned to the original positions,
wherein the LDPC code is an LDPC code having a code length N of 4,320 bits,
wherein the m bits are four bits, and the integer b is two,
wherein four bits of the code bits are mapped into one of 16 signal points that are determined in 16 QAM as one symbol,
wherein the storage means includes 8 columns storing 4×2 bits in the row direction and stores 4320/(4×2) bits in the column direction,
wherein the interchange means performs interchanging for allocation according to the allocation rule with the (#i+1)-th bit from the most significant bit of the code bits of 4×2 bits read in the row direction of the storage means being bit b#i and the (#i+1)-th bit from the most significant bit of the symbol bits of 4×2 bits of two consecutive symbols being bit y#i,
wherein the bit b 0 is allocated to the bit y 0 , the bit b 1 to the bit y 4 , the bit b 2 to the bit y 1 , the bit b 3 to the bit y 6 , the bit b 4 to the bit y 2 , the bit b 5 to the bit y 5 , the bit b 6 to the bit y 3 , and the bit b 7 to the bit y 7 ,
wherein a coded rate of the LDPC code having a code length of 4,320 bits is 1/2,
wherein a parity check matrix of the LDPC code is configured by arranging elements of 1's of an information matrix that is determined by a parity check matrix initial value table representing positions of elements of 1's of the information matrix of the parity check matrix that corresponds to a code length and an information length according to the coded rate for every 72 columns in the column direction at a period of 72 columns, and
wherein the parity check matrix initial value table is formed as follows:
142 150 213 247 507 538 578 828 969 1042 1107 1315
1509 1584 1612 1781 1934 2106 2117
3 17 20 31 97 466 571 580 842 983 1152 1226 1261
1392 1413 1465 1480 2047 2125 49 169 258 548 582 839 873
881 931 995 1145 1209 1639 1654 1776 1826 1865 1906 1956
148 393 396 486 568 806 909 965 1203 1256 1306 1371
1402 1534 1664 1736 1844 1947 2055
185 191 263 290 384 769 981 1071 1202 1357 1554
1723 1769 1815 1842 1880 1910 1926 1991
424 444 923 1679
91 436 535 978
362 677 821 1695
1117 1392 1454 2030
35 840 1477 2152
1061 1202 1836 1879
242 286 1140 1538
111 240 481 760
59 1268 1899 2144
737 1299 1395 2072
34 288 810 1903
232 1013 1365 1729
410 783 1066 1187
113 885 1423 1560
760 909 1475 2048
68 254 420 1867
283 325 334 970
168 321 479 554
378 836 1913 1928
101 238 964 1393
304 460 1497 1588
151 192 1075 1614
297 313 677 1303
329 447 1348 1832
582 831 984 1900
18. A data processing device comprising:
an interchange means that interchanges code bits of mb bits in accordance with an allocation rule used for allocating the code bits of an LDPC code to symbol bits representing a symbol and sets code bits after interchange as the symbol bits in a case where the code bits of the LDPC (low density parity check) code having a code length of N bits are written in a column direction of a storage means storing the code bits in a row direction and the column direction, the m bits of the code bits of the LDPC code read in the row direction are set as one symbol, a predetermined positive integer is set as b, the storage means stores the mb bits in the row direction and stores N/(mb) bits in the column direction, the code bits of the LDPC code are written in the column direction of the storage means and then are read in the row direction, and the code bits of the mb bits read in the row direction of the storage means form b symbols; and
a reverse interchanging means that performs a reverse interchanging process in which the positions of the code bits after interchange, which are acquired from a transmission device, are returned to the original positions,
wherein the LDPC code is an LDPC code having a code length N of 4,320 bits,
wherein the m bits are four bits, and the integer b is two,
wherein four bits of the code bits are mapped into one of 16 signal points that are determined in 16 QAM as one symbol,
wherein the storage means includes 8 columns storing 4×2 bits in the row direction and stores 4320/(4×2) bits in the column direction,
wherein the interchange means performs interchanging for allocation according to the allocation rule with the (#i+1)-th bit from the most significant bit of the code bits of 4×2 bits read in the row direction of the storage means being bit b#i and the (#i+1)-th bit from the most significant bit of the symbol bits of 4×2 bits of two consecutive symbols being bit y#i,
wherein the bit b 0 is allocated to the bit y 0 , the bit b 1 to the bit y 4 , the bit b 2 to the bit y 5 , the bit b 3 to the bit y 2 , the bit b 4 to the bit y 1 , the bit b 5 to the bit y 6 , the bit b 6 to the bit y 3 , and the bit b 7 to the bit y 7 ,
wherein a coded rate of the LDPC code having a code length of 4,320 bits is 7/12,
wherein a parity check matrix of the LDPC code is configured by arranging elements of 1's of an information matrix that is determined by a parity check matrix initial value table representing positions of elements of 1's of the information matrix of the parity check matrix that corresponds to a code length and an information length according to the coded rate for every 72 columns in the column direction at a period of 72 columns, and
wherein the parity check matrix initial value table is formed as follows:
96 246 326 621 668 748 874 965 1022 1108 1117 1142
1300 1469 1481 1627 1702
22 79 122 127 339 359 516 587 1025 1143 1294 1478
1484 1594 1651 1681 1794
80 426 429 506 599 810 892 1016 1117 1246 1277 1281
1316 1384 1713 1729 1753
15 145 182 305 451 563 570 635 781 827 983 1123
1204 1244 1311 1317 1348
11 157 164 292 301 360 636 859 871 895 1138 1164
1206 1268 1454 1613 1783
455 610 1123 1603
631 914 1424 1461
149 507 1275 1468
5 1078 1415 1735
169 772 775 1516
1207 1315 1683 1688
19 1053 1221 1260
933 1095 1597 1628
893 1209 1360 1740
1222 1486 1675 1737
897 1074 1651 1728
115 730 1363 1752
1552 1672 1734 1795
75 1087 1371 1712
123 438 839 1074
4 203 1407 1798
441 476 658 1400
380 1341 1741 1774
974 1487 1664 1756
7 273 834 1658
798 1475 1653 1686
12 1237 1539 1709
211 1494 1618 1624
367 1036 1390 1587
18 166 1645 1679
530 1092 1571 1707
588 1593 1689 1707
980 1104 1522 1701
1025 1510 1552 1683
270 340 1326 1770
19. A data processing device comprising:
an interchange means that interchanges code bits of mb bits in accordance with an allocation rule used for allocating the code bits of an LDPC code to symbol bits representing a symbol and sets code bits after interchange as the symbol bits in a case where the code bits of the LDPC (low density parity check) code having a code length of N bits are written in a column direction of a storage means storing the code bits in a row direction and the column direction, the m bits of the code bits of the LDPC code read in the row direction are set as one symbol, a predetermined positive integer is set as b, the storage means stores the mb bits in the row direction and stores N/(mb) bits in the column direction, the code bits of the LDPC code are written in the column direction of the storage means and then are read in the row direction, and the code bits of the mb bits read in the row direction of the storage means form b symbols; and
a reverse interchanging means that performs a reverse interchanging process in which the positions of the code bits after interchange, which are acquired from a transmission device, are returned to the original positions,
wherein the LDPC code is an LDPC code having a code length N of 4,320 bits,
wherein the m bits are four bits, and the integer b is two,
wherein four bits of the code bits are mapped into one of 16 signal points that are determined in 16 QAM as one symbol,
wherein the storage means includes 8 columns storing 4×2 bits in the row direction and stores 4320/(4×2) bits in the column direction,
wherein the interchange means performs interchanging for allocation according to the allocation rule with the (#i+1)-th bit from the most significant bit of the code bits of 4×2 bits read in the row direction of the storage means being bit b#i and the (#i+1)-th bit from the most significant bit of the symbol bits of 4×2 bits of two consecutive symbols being bit y#i,
wherein the bit b 0 is allocated to the bit y 0 , the bit b 1 to the bit y 4 , the bit b 2 to the bit y 5 , the bit b 3 to the bit y 2 , the bit b 4 to the bit y 1 , the bit b 5 to the bit y 6 , the bit b 6 to the bit y 3 , and the bit b 7 to the bit y 7 ,
wherein a coded rate of the LDPC code having a code length of 4,320 bits is 2/3,
wherein a parity check matrix of the LDPC code is configured by arranging elements of 1's of an information matrix that is determined by a parity check matrix initial value table representing positions of elements of 1's of the information matrix of the parity check matrix that corresponds to a code length and an information length according to the coded rate for every 72 columns in the column direction at a period of 72 columns, and
wherein the parity check matrix initial value table is formed as follows:
56 291 315 374 378 665 682 713 740 884 923 927 1193
1203 1293 1372 1419 1428
1 17 113 402 406 504 559 597 686 697 817 878 983
1007 1034 1142 1231 1431
2 205 350 428 538 605 866 973 1008 1182 1252 1303
1319 1337 1346 1387 1417 1422
50 158 244 424 455 597 830 889 900 945 978 1040
1052 1059 1101 1150 1254 1382 41 53 269 316 449 604 704
752 937 952 1021 1031 1044 1068 1104 1265 1327 1348 601
911 1020 1260
151 674 732 1240
1099 1250 1348 1366
1115 1124 1394 1414
66 250 875 1040
525 603 916 1402
529 561 913 1089
1110 1243 1280 1372
137 656 1316 1369
5 458 1043 1381
1122 1171 1187 1335
18 130 312 1209
30 534 705 1294
272 727 955 1192
925 1287 1385 1437
11 446 1281 1408
614 716 787 1340
615 1147 1411 1416
284 865 1151 1414
202 689 1088 1144
459 633 838 941
46 301 1229 1367
476 1031 1120 1418
138 336 560 1419
168 357 536 938
1001 1052 1162 1414
349 1039 1353 1426
146 203 530 549
510 545 979 1108
479 1069 1106 1244
743 1019 1275 1348
427 721 1023 1435
73 842 1296 1435
323 1106 1140 1428
1074 1235 1353 1391
20. A data processing device comprising:
an interchange means that interchanges code bits of mb bits in accordance with an allocation rule used for allocating the code bits of an LDPC code to symbol bits representing a symbol and sets code bits after interchange as the symbol bits in a case where the code bits of the LDPC (low density parity check) code having a code length of N bits are written in a column direction of a storage means storing the code bits in a row direction and the column direction, the m bits of the code bits of the LDPC code read in the row direction are set as one symbol, a predetermined positive integer is set as b, the storage means stores the mb bits in the row direction and stores N/(mb) bits in the column direction, the code bits of the LDPC code are written in the column direction of the storage means and then are read in the row direction, and the code bits of the mb bits read in the row direction of the storage means form b symbols; and
a reverse interchanging means that performs a reverse interchanging process in which the positions of the code bits after interchange, which are acquired from a transmission device, are returned to the original positions,
wherein the LDPC code is an LDPC code having a code length N of 4,320 bits,
wherein the m bits are four bits, and the integer b is two,
wherein four bits of the code bits are mapped into one of 16 signal points that are determined in 16 QAM as one symbol,
wherein the storage means includes 8 columns storing 4×2 bits in the row direction and stores 4320/(4×2) bits in the column direction,
wherein the interchange means performs interchanging for allocation according to the allocation rule with the (#i+1)-th bit from the most significant bit of the code bits of 4×2 bits read in the row direction of the storage means being bit b#i and the (#i+1)-th bit from the most significant bit of the symbol bits of 4×2 bits of two, consecutive symbols being bit y#i,
wherein the bit b 0 is allocated to the bit y 0 , the bit b 1 to the bit y 4 , the bit b 2 to the bit y 5 , the bit b 3 to the bit y 2 , the bit b 4 to the bit y 1 , the bit b 5 to the bit y 6 , the bit b 6 to the bit y 3 , and the bit b 7 to the bit y 7 ,
wherein a coded rate of the LDPC code having a code length of 4,320 bits is 3/4,
wherein a parity check matrix of the LDPC code is configured by arranging elements of 1's of an information matrix that is determined by a parity check matrix initial value table representing positions of elements of 1's of the information matrix of the parity check matrix that corresponds to a code length and an information length according to the coded rate for every 72 columns in the column direction at a period of 72 columns, and
wherein the parity check matrix initial value table is formed as follows:
3 14 207 304 349 414 577 587 748 761 772 855 920
976 1009 1058 1069
4 61 81 86 136 146 257 392 402 594 812 959 972 1037
1055 1064 1076
0 68 160 237 437 512 624 629 652 702 818 858 943
998 1035 1044 1064
10 42 159 215 254 320 373 382 410 492 630 887 889
911 916 975 1069
12 32 298 302 318 425 558 621 670 779 964 967 970
975 1054 1067 1072
124 381 715 981
503 610 633 1030
321 874 900 1020
509 817 902 978
3 118 688 911
515 644 848 1067
13 75 721 970
9 464 756 1023
26 219 304 672
5 310 410 695
0 7 267 1040
76 822 873 1043
7 129 1010 1065
115 156 714 1003
163 480 505 1079
238 601 743 1046
216 702 738 912
13 20 166 979
11 14 261 1051
186 476 595 843
13 237 451 532
7 11 594 738
10 225 495 851
520 675 1018 1045
9 352 514 543
60 917 1071 1074
471 556 673 1062
345 350 1043 1076
5 539 788 1061
704 851 883 1049
211 233 242 1072
9 1047 1057 1076
18 172 473 1042
365 488 921 968
211 216 554 824
1 709 923 1074
576 647 901 963
71 676 1053 1073
265 738 958 969
66 274 774 811