Shuffle pattern generating circuit, processor, shuffle pattern generating method, and instruction sequence
View Patent ↗Based on an input index sequence ( 702 ) composed of four indices (each having a bit width of 8 bits), a shift-copier generates an index sequence ( 902 ) by shifting each index leftward by 1 bit and making two copies of each index, and outputs the generated index sequence ( 902 ). An adder generates a shuffle pattern ( 703 ) by adding 1, 0, 1, 0, 1, 0, 1 and 0 to the indices in the index sequence ( 902 ) from left to right, and outputs the generated shuffle pattern ( 703 ).
1. A shuffle pattern generating circuit comprising:
a shift-copier that generates an index sequence by: receiving an input index sequence composed of a plurality of indices, and a signal indicating a number of bits and a number of copies; shifting each index in the input index sequence leftward by the number of bits; and
making the number of copies of each index in the input index sequence, and outputs the generated index sequence; and
an adder that receives the index sequence output by the shift-copier and a signal indicating an additional value to be added to each index in the index sequence output by the shift-copier, and adds the additional value to each index in the index sequence output by the shift-copier.
2. The shuffle pattern generating circuit of claim 1 , wherein
the additional value is different for each copy made from a same index in the input index sequence.
3. The shuffle pattern generating circuit of claim 2 , wherein
the number of the copies is N (where N is an integer equal to or greater than 2), and
the additional value to be added to one of the copies made from a same index in the input index sequence is 0, and the additional value to be added to each of the remaining N−1 copies is an integer ranging from 1 to N−1.
4. The shuffle pattern generating circuit of claim 1 , further comprising:
a bit width changer that receives a signal indicating a bit width of each index in the input index sequence, and changes a bit width of each index to the bit width indicated by the signal.
5. The shuffle pattern generating circuit of claim 1 , wherein
the shift-copier makes the copies of each index after shifting each index leftward, or shifts each index leftward after making the copies of each index.
6. A processor including the shuffle pattern generating circuit of claim 1 , comprising:
an instruction decoder that decodes an input instruction and generates a control signal according to the instruction; and
a register file that provides data to the shuffle pattern generating circuit and stores data provided by the shuffle pattern generating circuit according to the control signal, wherein
the signal received by the shuffle pattern generating circuit is the control signal.
7. A shuffle pattern generating method comprising:
a shift-copier step of generating an index sequence by: receiving an input index sequence composed of a plurality of indices, and a signal indicating a number of bits and a number of copies; shifting each index in the input index sequence leftward by the number of bits; and making the number of copies of each index in the input index sequence, and outputting the generated index sequence; and
an adder step of receiving the index sequence output by the shift-copier step and a signal indicating an additional value to be added to each index in the index sequence output by the shift-copier step, and adding the additional value to each index in the index sequence output by the shift-copier step.
8. The shuffle pattern generating method of claim 7 , wherein
in the shift-copier step, the copies of each index are made after each index is shifted leftward, or each index is shifted leftward after the copies of each index are made.
9. An instruction sequence comprising:
an instruction to receive an input index sequence composed of a plurality of indices, and control data indicating a number of bits, a number of copies, and an additional value to be added to each index;
an instruction to shift each index leftward by the number of bits;
an instruction to make the number of copies of each index; and
an instruction to add the additional value to each index, and to output each index after the addition.
10. The instruction sequence of claim 9 , wherein
the additional value is different for each copy made from a same index in the input index sequence.
11. The instruction sequence of claim 10 , wherein
the number of the copies is N (where N is an integer equal to or greater than 2), and
the additional value to be added to one of the copies made from a same index in the input index sequence is 0, and the additional value to be added to each of the remaining N−1 copies is an integer ranging from 1 to N−1.
12. The instruction sequence of claim 9 , wherein
the control data indicates a bit width of each index, and
the set of instructions further comprising:
an instruction to change a bit width of each index to the bit width indicated by the control data, and to output each index after changing the bit width.