CLOCK GENERATOR
A clock generator or oscillating circuit is provided to generate a clock signal with high Power Supply Rejection Ratio (PSSR), or a stable clock signal that is resistant to variations in the power supply. The clock generator or oscillating circuit may also adjust the clock period (T) of the clock signal, either or both upwards and downwards, around its central value to compensate fabrication process variations.
1 . A device comprising:
a clock generating circuit including:
a first comparator circuit and a second comparator circuit which work complementary to each other to generate a first signal and a second signal having an opposite phase to the first signal;
a first reference circuit including a first capacitor and a first resistance to produce, in response to the second signal, a first reference voltage supplied to the first comparator circuit; and
a second reference circuit including a second capacitor and a second resistance to produce, in response to the first signal, a second reference voltage supplied to the second comparator circuit.
2 . The device as claimed in claim 1 , wherein the clock generating circuit further includes:
a first preceding circuit including a third capacitor and a third resistance to produce, in response to the first signal, a first comparison voltage compared by the first comparator circuit with the first reference voltage; and
a second preceding circuit including a fourth capacitor and a fourth resistor to produce, in response to the second signal, a second comparison voltage compared by the second comparator with the second reference voltage.
3 . The device as claimed in claim 1 , wherein the first reference circuit and the second reference circuit are substantially same in a circuit structure as each other.
4 . The device as claimed in claim 2 , wherein the first preceding circuit and the second preceding circuit are substantially same in a circuit structure as each other.
5 . The device as claimed in claim 1 , wherein the first reference circuit of the clock generating circuit further includes:
a first transistor coupled between a first power supply line and a reference input node of the first comparator and including a gate supplied with the second signal;
a second transistor coupled between the reference input node of the first comparator and a second power supply line and including a gate supplied with the second signal;
the first capacitor coupled between the reference input node of the first comparator and the second power supply line; and
the first resistance coupled between the reference input node of the first comparator and the second transistor;
and wherein the second reference circuit of the clock generating circuit further includes:
a third transistor coupled between the first power supply line and a reference input node of the second comparator and including a gate supplied with the first signal;
a second transistor coupled between the reference input node of the second comparator and a second power supply line and including a gate supplied with the first signal;
the second capacitor coupled between the reference input node of the second comparator and the second power supply line; and
the second resistance coupled between the reference input node of the second comparator and the fourth transistor.
6 . The device as claimed in claim 1 , further comprising:
a memory;
a circuit controlling the memory in response to the first and second signal supplied from the clock generating circuit.
7 . The device as claimed in claim 1 , wherein the memory includes a NAND flash memory.
8 . A device comprising:
a clock generating circuit including:
a first comparator circuit and a second comparator circuit which work complementary to each other to generate a first signal and a second signal having an opposite phase to the first signal;
a first reference circuit producing, in response to the second signal, a first reference voltage supplied to the first comparator circuit, and including:
a first transistor coupled between a first power supply line and a reference input node of the first comparator and including a gate supplied with the second signal;
a second transistor coupled between the reference input node of the first comparator and a second power supply line and including a gate supplied with the second signal;
a first capacitor coupled between the reference input node of the first comparator and the second power supply line; and
a first resistance coupled between the reference input node of the first comparator and the second transistor.
9 . The device as claimed in claim 8 , wherein the clock generating circuit further includes:
a first preceding circuit producing, in response to the first signal, a first comparison voltage compared by the first comparator circuit with the first reference voltage, and including:
a second transistor coupled between the first power supply line and a comparison node of the first comparator circuit and including a gate supplied with the first signal;
a second transistor coupled between the comparison node of the first comparator circuit and the second power supply line and including a gate supplied with the first signal;
a second capacitor coupled between the comparison node of the first comparator circuit and the second power supply line; and
a second resistance coupled between the first transistor and the comparison node of the first comparator circuit.
10 . The device as claimed in claim 8 , further comprising:
a memory;
a circuit controlling the memory in response to the first and second signal supplied from the clock generating circuit.
11 . The device as claimed in claim 10 , wherein the memory includes a NAND flash memory.
12 . A device comprising:
a clock generating circuit including:
a first comparator circuit and a second comparator circuit which work complementary to each other to generate a first signal and a second signal having an opposite phase to the first signal;
a first reference circuit producing, in response to the second signal, a first reference voltage supplied to the first comparator circuit, the first reference voltage varying in a voltage level; and
a second reference circuit producing, in response to the first signal, a second reference voltage supplied to the second comparator circuit, the second reference voltage varying in a voltage level.
13 . The device as claimed in claim 12 , wherein a first time period that the first reference voltage varies from a first voltage level to a second voltage level is shorter than a second time period that the first reference voltage varies from the second voltage level to the first voltage level, and
a third time period that the second reference voltage varies from the first voltage level to the second voltage level is shorter than a fourth time period that the second reference voltage varies from the second voltage level to the first voltage level.
14 . The device as claimed in claim 12 , wherein the clock generating circuit further includes:
a first preceding circuit producing, in response to the first signal, a first comparison voltage compared by the first comparator circuit with the first reference voltage, the first comparison voltage varying in a voltage level;
a second preceding circuit producing, in response to the second signal, a second comparison voltage compared by the second comparator with the second reference voltage, the second comparison voltage varying in a voltage level.
15 . The device as claimed in claim 14 , wherein a fifth time period that the first comparison voltage varies from a third voltage level to the second voltage level is identical to a first time period that the first reference voltage varies from a first voltage level to the second voltage level, and
a sixth time period that the second comparison voltage varies from the third voltage level to the second voltage level is identical to a third time period that the second reference voltage varies from the first voltage level to the second voltage level.
16 . The device as claimed in claim 15 , wherein the first signal takes a first level in the fifth time period, and the second signal takes a second level different from the first level in the fifth time period, and
wherein the first signal takes the first level in the sixth time period, and the second signal takes the first level in the sixth time period.