Semiconductor device having penetrating electrodes each penetrating through semiconductor chip

1. A semiconductor device comprising:

a semiconductor substrate including a first surface and a second surface opposite to each other; and

a plurality of alignment marks, the plurality of alignment marks comprising a plurality of first through-substrate vias, each of the plurality of first through-substrate vias penetrating through the semiconductor substrate from the first surface to the second surface, each of the plurality of first through-substrate vias including a first bump that protrudes from the first surface of the semiconductor substrate.

2. The semiconductor device as claimed in claim 1 , further comprising a plurality of second through-substrate vias each penetrating through the semiconductor substrate from the first surface to the second surface, wherein

the second through-substrate vias transmit corresponding signals, and

the first through-substrate vias are arranged narrower in pitch than the second through-substrate vias.

3. The semiconductor device as claimed in claim 2 , further comprising:

a plurality of second bumps provided over the second surface of the semiconductor substrate,

wherein each of the second bumps is vertically aligned with an associated one of the second through-substrate vias.

4. The semiconductor device as claimed in claim 1 , further comprising:

a first wiring layer provided over the second surface of the semiconductor substrate; and

a second surface alignment mark provided as the first wiring layer, the second-surface alignment mark being vertically aligned with the first surface alignment mark.

5. The semiconductor device as claimed in claim 2 , further comprising a plurality of third through-substrate vias each penetrating through the semiconductor substrate from the first surface to the second surface, wherein

the second through-substrate vias are arranged in a first direction in a central portion of the semiconductor substrate, and

the third through-substrate vias are arranged in a second direction in an edge portion of the semiconductor substrate.

6. The semiconductor device as claimed in claim 5 , wherein the third through-substrate vias are arranged substantially equal in pitch to the second through-substrate vias.

7. The semiconductor device as claimed in claim 1 , further comprising:

a first wiring layer provided over the second surface of the semiconductor substrate; and

a first conductive pattern provided as the first wiring layer,

wherein the first through-substrate vias are connected in common to the first conductive pattern.

8. The semiconductor device as claimed in claim 1 , further comprising a plurality of fourth through-substrate vias each penetrating through the semiconductor substrate from the first surface to the second surface, each of the fourth through-substrate vias including a fourth bump that protrudes from the first surface of the semiconductor substrate, wherein

the fourth bumps serve as second surface alignment mark on the first surface of the semiconductor substrate,

the first surface alignment mark is arranged at a first corner portion on the first surface of the semiconductor substrate, and

the second surf ace alignment mark is arranged at a second corner portion on the first surface of the semiconductor substrate.

9. The semiconductor device as claimed in claim 8 , wherein

the first and second corner portions are positioned at diagonally opposite corners, and

a layout of the first bumps is different from a layout of the fourth bumps.

10. The semiconductor device as claimed in claim 8 , further comprising an auxiliary alignment mark arranged at a third corner portion on the first surface of the semiconductor substrate,

wherein the auxiliary alignment mark includes a fifth bump of a fifth through-substrate via penetrating through the semiconductor substrate from the first surface to the second surface.

11. A semiconductor device comprising:

a semiconductor substrate;

first and second conductive patterns provided over a surface of the semiconductor substrate;

a plurality of alignment marks, the plurality of alignment marks comprising at least one of a plurality of first through-substrate vias and a plurality of second through-substrate vias, each of the plurality of first through-substrate vias and each of the plurality of second through-substrate vias penetrating through the semiconductor substrate, the plurality of first through-substrate vias being arranged in a first pitch in a first corner portion of the semiconductor substrate and being coupled in common to the first conductive pattern,

the plurality of second through-substrate vias being arranged in the first pitch in a second corner portion of the semiconductor substrate and being coupled in common to the second conductive pattern; and

a plurality of third through-substrate vias each penetrating through the semiconductor substrate, the plurality of third through-substrate vias being arranged in a second pitch that is greater than the first pitch and supplied respectively with signals.

12. The semiconductor device as claimed in claim 11 , wherein

the first and second corner portions are positioned at diagonally opposite corners, and

a layout of first through-substrate vias is different from a layout of the second through-substrate vias.

13. The semiconductor device as claimed in claim 12 , further comprising third and fourth conductive patterns, wherein

the third conductive pattern is vertically overlap with the first through-substrate vias,

the fourth conductive pattern is vertically overlapped with the second through-substrate vias.

14. The semiconductor device as claimed in claim 13 , wherein

the first and second conductive patterns and the third and fourth conductive patterns are formed on different wiring layers,

the third conductor pattern is vertically covered with the first conductor pattern, and

the fourth conductor pattern is vertically covered with the second conductor pattern.