BIPOLAR TRANSISTOR WITH LOWERED 1/F NOISE
In a bipolar transistor, a thin gate oxide, preferably less than 600 Å, is formed over the base surface region between the emitter and collector. A conductive gate, such as doped polysilicon, is then formed over the gate oxide and biased at the emitter voltage. In the example of a PNP transistor, when the emitter is forward biased with respect to the base to turn the transistor on, the gate is at a positive potential relative to the base. This causes the holes in the base conducting the emitter-collector current to be repelled away from the surface, and the electrons in the base to be attracted to the surface, so that more of the emitter-collector current flows deeper into the base. Thus, the effect of defects at the base surface is mitigated, and 1/f noise is reduced. The invention is equally applicable to PNP and NPN transistors. Other benefits result.
1 . A bipolar transistor comprising:
an emitter of a first conductivity type;
a collector of the first conductivity type;
a base of a second conductivity type between the emitter and the collector, the base having a surface portion, the emitter, base, and collector forming a bipolar transistor;
a gate dielectric formed over at least a portion of the surface portion of the base between the emitter and collector; and
a conductive gate formed over the gate dielectric, the gate being coupled to a voltage potential, the gate dielectric and voltage potential being such that, when the transistor is turned on by forward biasing the emitter relative to the base, a resulting electric field generated by the gate forces more minority current in the base to be conducted deeper beneath the surface portion of the base between the emitter and collector.
2 . The transistor of claim 1 wherein the transistor is a lateral transistor.
3 . The transistor of claim 1 wherein the gate dielectric is less than 1000 Angstroms thick.
4 . The transistor of claim 1 wherein the gate dielectric is less than 600 Angstroms thick.
5 . The transistor of claim 1 wherein the gate dielectric is less than 300 Angstroms thick.
6 . The transistor of claim 1 wherein the gate dielectric is thermally grown.
7 . The transistor of claim 1 wherein the gate is coupled to the emitter so as to have the same potential as the emitter.
8 . The transistor of claim 1 wherein the transistor is a PNP type, and the gate is connected to a voltage more positive than the base.
9 . The transistor of claim 1 wherein the transistor is an NPN type, and the gate is connected to a voltage more negative than the base.
10 . The transistor of claim 1 wherein the resulting electric field generated by the gate reduces 1/f noise in the transistor.
11 . The transistor of claim 1 wherein the resulting electric field generated by the gate lowers a 1/f noise corner of the transistor.
12 . The transistor of claim 1 wherein the base is epitaxially grown.
13 . A method of operating a bipolar transistor, the transistor comprising an emitter of a first conductivity type, a collector of the first conductivity type, and a base of a second conductivity type between the emitter and the collector, the base having a surface portion between the emitter and the collector, the method comprising:
turning on the transistor by forward biasing the emitter relative to the base; and
applying a voltage to a conductive gate, insulated from the surface portion by a gate dielectric, such that minority carriers in the base are repelled from the surface portion by an electric field created between the base and the gate to force more minority current in the base to be conducted deeper beneath the surface portion of the base between the emitter and collector.
14 . The method of claim 13 wherein the gate dielectric does not extend completely over the emitter and collector.
15 . The method of claim 13 wherein the transistor is a lateral transistor.
16 . The method of claim 13 wherein the gate dielectric is less than 1000 Angstroms thick.
17 . The method of claim 13 wherein the gate dielectric is less than 600 Angstroms thick.
18 . The method of claim 13 further comprising thermally growing the gate dielectric.
19 . The method of claim 13 wherein the step of applying the voltage to the gate comprises coupling the gate to the emitter so as to have the same potential as the emitter.
20 . The method of claim 13 wherein the transistor is a PNP type, and the gate is connected to a voltage more positive than the base.
21 . The method of claim 13 wherein the transistor is an NPN type, and the gate is connected to a voltage more negative than the base.
22 . The method of claim 13 wherein the resulting electric field generated by the gate reduces 1/f noise in the transistor.
23 . The method of claim 13 wherein the resulting electric field generated by the gate lowers a 1/f noise corner of the transistor.