Methods and systems for determining characteristics of a sequence of n-state symbols
Maximum length properties of n-state sequences of n-state symbols with n=2 or n>2 are tested. Checkwords are generated from p consecutive n-state symbols in a sequence of n-state symbols which may overlap by (p−1) n-state symbols. If a sequence has n p −1 n-state symbols in which 2 consecutive checkwords overlap in (p−1) n-state symbols and each checkword formed in the extended sequence is unique, then the sequence is a maximum length n-state sequence. An n-state feedback shift register based sequence generator with p n-state register elements is tested on the content of the shift register for n p −1 cycles. If the shift register content is not repeated the sequence is maximum length. Generation of a sequence is stopped when the content repeats. Non-reversible n-state inverters and non-reversible n-state logic functions are applied to generate n-state sequences.
1. A method for testing a property of a sequence of at least k n-state symbols with n an integer greater than 1 and k an integer greater than 2, each n-state symbol being represented by a signal, comprising:
a processor selecting a first n-state inverter from a plurality of n-state inverters and implementing the first n-state inverter in a shift register of p n-state shift register elements with feedback with p an integer greater than 1 and at least one n-state switching function;
the processor generating n-state symbols in the sequence by a sequence generator that is defined by a first configuration that includes the n-state feedback shift register of p n-state shift register elements, the first n-state inverter and the at least one n-state switching function, wherein each generated n-state symbol corresponds with a content of the shift register of p n-state symbols, wherein the processor generates a first n-valued symbol and stores a corresponding first content of the shift register of p n-state symbols in a memory;
the processor generating a k th n-valued symbol in the sequence of at least k n-state symbols based on a k th content of the shift register; and
the processor comparing the k th shift register content of p n-state symbols with the first content of the shift register of p n-state symbols corresponding with generating the first n-state symbol in the sequence of n-state symbols to determine if the first content of the shift register of p n-valued symbols is repeated to decide to generate the next symbol in the sequence of n-state symbols.
2. The method of claim 1 , wherein n>2.
3. The method of claim 1 , further comprising:
the processor stopping generating the sequence of n-state symbols after a repeat of the first content of the p n-state shift registers is detected.
4. The method of claim 3 , further comprising:
the processor reconfiguring the sequence generator that is defined by the first configuration including replacing the first n-state inverter with a second n-state inverter and initializing the shift register and restarting the generation of the sequence of n-state symbols.
5. The method of claim 1 , wherein the sequence generator that is defined by the first configuration generates n p −1 n-state symbols in the sequence of n-state symbols without repeating the first content of the shift register of p n-valued symbols.
6. The method of claim 5 , further comprising:
placing the first configuration of the sequence generator in a catalog of sequence generators.
7. The method of claim 1 , wherein the comparing is performed by the processor comparing representative values of contents of the shift register.
8. The method of claim 1 , further comprising:
receiving the sequence of k n-state symbols by a second processor;
the second processor creating a plurality of checkwords from the k n-state symbols; and
the second processor determining if a checkword in the plurality of checkwords is repeated.
9. The method of claim 1 , further comprising:
a communication system to process signals representing the sequence of k n-state symbols.
10. The method of claim 6 , further comprising:
selecting the sequence generator defined by the first configuration from the catalog and applying the sequence generator defined by the first configuration in a communication system.
11. A system to determine a property of a sequence of k n-state symbols with n equal to or greater than 2 and k>2, each n-state symbol being represented by a signal, comprising:
a memory enabled to store data in and to retrieve data from including instructions;
a processor configured to execute instructions to perform the steps:
selecting a first n-state inverter from a plurality of n-state inverters and implementing the first n-state inverter in an n-state feedback shift register of p n-state shift register elements;
generating n-state symbols in the sequence by a sequence generator that is defined by a first configuration that includes the n-state feedback shift register of p n-state shift register elements and at least one n-state switching function and the first n-state inverter, wherein each generated n-state symbol corresponds with a content of the shift register of p n-state symbols and p is an integer greater than 1;
storing a first content of the shift register of p n-state symbols corresponding to generating a first n-state symbol in the memory;
generating a k th n-state symbol in the sequence corresponding to a k th content of the shift register of p n-state symbols; and
comparing the k th content of the shift register of p n-state symbols with the first content of the shift register of p n-state symbols corresponding with generating the first n-state symbol in the sequence of n-state symbols to decide to generate a next symbol in the sequence of n-state symbols.
12. The system of claim 11 , wherein n>2.
13. The system of claim 11 , further comprising:
the processor being configured to stop generating the sequence of n-state symbols after a repeat of the first content of the shift register of p n-state symbols is detected.
14. The system of claim 13 , further comprising:
the processor being configured to reconfigure the n-state feedback shift register defined-by the first configuration by replacing the first n-state inverter with a second n-state inverter and initializing the shift register and restarting the generation of the sequence of n-state symbols.
15. The system of claim 11 , further comprising:
the processor being configured to detect a first occurrence of a repeat of a previous shift register content related to a start of the sequence.
16. The system of claim 11 , wherein the_n-state feedback shift register defined sequence generator is configured to generate n p −1 n-state symbols in the sequence of n-state symbols without repeating any content of the shift register.
17. The system of claim 11 , further comprising:
a second processor is configured to execute instructions to perform the steps:
receiving signals representing the sequence of k n-state symbols;
creating a plurality of checkwords from the sequence of k n-state symbols; and
determining if a checkword in the plurality of checkwords is repeated.
18. The system of claim 11 , further comprising:
a communication system implementing the sequence generator in the first configuration.
19. The system of claim 11 , further comprising a memory storing a catalog of configurations of n-state sequence generators.
20. The system of claim 19 , wherein a processor implements an n-state sequence generator in the first configuration selected from the catalog stored in the memory.