Method of fabricating non-volatile memory device

1. A method of fabricating a non-volatile memory, comprising:

sequentially forming a tunneling dielectric layer and a first patterned conductive layer on a substrate;

sequentially stacking a patterned inter-gate dielectric layer and a second patterned conductive layer on a first surface of the first patterned conductive layer and exposing a second surface of the first patterned conductive layer, the second surface being adjacent to the first surface;

covering the substrate by a passivation layer and exposing a first sidewall of the first patterned conductive layer;

forming a recess on the first sidewall of the first patterned conductive layer, such that the first sidewall has a sharp corner;

forming a source region in the substrate adjacent to the first sidewall of the first patterned conductive layer;

removing a portion of the passivation layer on the second surface, such that the sharp corner of the first patterned conductive layer is exposed; and

forming a drain region in the substrate outside a second sidewall of the first patterned conductive layer.

2. The method of fabricating the non-volatile memory as recited in claim 1 , wherein the step of forming the passivation layer comprises:

forming a buffer layer on the second surface of the first patterned conductive layer; and

forming a spacer and a shielding layer on the buffer layer and the substrate at a first side of the second patterned conductive layer, wherein the spacer is located between the second patterned conductive layer and the shielding layer.

3. The method of fabricating the non-volatile memory as recited in claim 2 , wherein the step of removing the portion of the passivation layer on the second surface comprises removing the shielding layer and the underlying buffer layer, so as to expose the sharp corner of the first patterned conductive layer.

4. The method of fabricating the non-volatile memory as recited in claim 2 , wherein the step of forming the first patterned conductive layer, the patterned inter-gate dielectric layer, the second patterned conductive layer, the buffer layer, the spacer, and the shielding layer comprises:

forming a first conductive layer on the tunneling dielectric layer and exposing a portion of the tunneling dielectric layer;

forming the patterned inter-gate dielectric layer and the second patterned conductive layer on the first conductive layer;

removing a portion of the first conductive layer at the first side of the second patterned conductive layer;

forming a buffer material layer on the first conductive layer at a second side of the second patterned conductive layer;

forming the spacer and the shielding layer on a sidewall of the second patterned conductive layer, a sidewall of the patterned inter-gate dielectric layer, and the second sidewall of the first patterned conductive layer and exposing the buffer material layer at the second side of the second patterned conductive layer; and

removing the buffer material layer exposed by the shielding layer at the second side of the second patterned conductive layer and removing the first conductive layer located under the buffer material layer, the remaining first conductive layer being the first patterned conductive layer, the remaining buffer material layer being the buffer layer.

5. The method of fabricating the non-volatile memory as recited in claim 4 , wherein a method of forming the shielding layer comprises:

forming a shielding material layer on the substrate; and

forming a first mask layer on the substrate, the first mask layer having an opening, the opening exposing the shielding material layer at the second side of the second patterned conductive layer; and

performing an anisotropic etching process on the shielding material layer exposed by the opening to expose the buffer layer.

6. The method of fabricating the non-volatile memory as recited in claim 5 , wherein a material of the shielding material layer is different from a material of the spacer.

7. The method of fabricating the non-volatile memory as recited in claim 5 , wherein a material of the shielding material layer comprises silicon oxide, silicon carbide, silicon carbonitride, silicon carbon oxide, silicon carbo-oxynitride, or a combination thereof.

8. The method of fabricating the non-volatile memory as recited in claim 5 , wherein a material of the shielding material comprises silicon oxide using tetraethyl orthosilicate as a reactive gas.

9. The method of fabricating the non-volatile memory as recited in claim 4 , wherein a material of the buffer material layer comprises silicon oxide.

10. The method of fabricating the non-volatile memory as recited in claim 4 , wherein a method of forming the buffer material layer comprises performing a thermal oxidization process.

11. The method of fabricating the non-volatile memory as recited in claim 1 , wherein a method of forming the recess on the first sidewall of the first patterned conductive layer comprises performing an isotropic etching process.

12. The method of fabricating the non-volatile memory as recited in claim 1 , before forming the drain region, the method further comprising:

removing the tunneling dielectric layer not covered by the first patterned conductive layer and exposing a surface of the substrate, wherein the spacer, the second patterned conductive layer, the patterned inter-gate dielectric layer, the first patterned conductive layer, and the tunneling dielectric layer together constituting a first gate stack;

forming a first dielectric layer on the substrate, the first dielectric layer covering the spacer, the second patterned conductive layer, and the source region;

forming a second dielectric layer on the substrate between the drain region and the first gate stack; and

forming an erasing gate above the source region and forming a selecting gate on the second dielectric layer.

13. The method of fabricating the non-volatile memory as recited in claim 12 , wherein the first gate stack further comprises a cap layer located on the second conductive layer.

14. The method of fabricating the non-volatile memory as recited in claim 12 , further comprising forming a second gate stack on the substrate when the first gate stack is formed, the first and second gate stacks constituting a gate stack set, the method further comprising forming another drain region at a side of the second gate stack when the drain region is formed.