IP Library Granted Patent US 9,202,547
Granted Patent B2
US 9,202,547 · App. 13/832,278 · Granted Dec 1, 2015

Managing disturbance induced errors

Inventors: Prashant S. Damle (Portland, OR); Frank T. Hady (Portland, OR); Paul D. Ruby (Folsom, CA); Kiran Pangal (Fremont, CA); Sowmiya Jayachandran (Portland, OR)
Assignee: Intel Corporation
G11C11/406G11C16/3431
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Quick Facts
Patent No.
US 9,202,547
App. No.
13/832,278
Granted
Dec 1, 2015
Kind
B2
Abstract

In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.

Claims (43)

1. A method comprising:

determining at a controller that one or more neighboring memory cells associated with a target memory cell are to be refreshed;

generating a command associated with refreshing the one or more neighboring memory cells; and

transferring the command from the memory controller to a memory device containing the target memory cell.

2. The method of claim 1 , wherein the command directs the memory device to refresh the neighboring cells.

3. The method of claim 1 , wherein the command directs the memory device to return one or more addresses associated with the neighboring memory cells.

4. The method of claim 3 , further comprising:

acquiring the one or more addresses associated with the neighboring memory cells from the memory device.

5. The method of claim 4 , further comprising:

refreshing one or more neighboring memory cells associated with the acquired one or more addresses.

6. The method of claim 1 , wherein determining further comprises:

generating a random number for an access of the target memory cell; and

determining whether the generated random number matches certain criteria.

7. The method of claim 1 , wherein determining further comprises:

maintaining a count associated with accessing the target memory cell; and

determining whether the maintained count matches certain criteria.

8. One or more tangible non-transitory computer-readable mediums storing executable instructions for execution by processing logic, the medium storing:

one or more instructions for determining at a controller that one or more neighboring memory cells associated with a target memory cell are to be refreshed;

one or more instructions for generating a command associated with refreshing the one or more neighboring memory cells; and

one or more instructions for transferring the command from the memory controller to a memory device containing the target memory cell.

9. The medium of claim 8 , wherein the command directs the memory device to refresh the neighboring cells.

10. The medium of claim 8 , wherein the command directs the memory device to return one or more addresses associated with the neighboring memory cells.

11. The medium of claim 10 , further storing:

one or more instructions for acquiring the one or more addresses associated with the neighboring memory cells from the memory device.

12. The medium of 11 , further storing:

one or more instructions for refreshing one or more neighboring memory cells associated with the acquired one or more addresses.

13. The medium of claim 8 , further storing:

one or more instructions for generating a random number for an access of the target memory cell; and

one or more instructions for determining whether the generated random number matches certain criteria.

14. The medium of claim 8 , further storing:

one or more instructions for maintaining a count associated with accessing the target memory cell; and

one or more instructions for determining whether the maintained count matches certain criteria.

15. A system comprising:

a memory device having a target memory cell and one or more neighboring memory cells associated with the target memory cell; and

a controller to:

determine that one or more neighboring memory cells are to be refreshed,

generate a command associated with refreshing the one or more neighboring memory cells, and

transfer the command to the memory device.

16. The system of claim 15 , wherein the command directs the memory device to refresh the neighboring cells.

17. The system of claim 15 , wherein the command directs the memory device to return one or more addresses associated with the neighboring memory cells.

18. The system of claim 17 , wherein the controller is to further:

acquire the one or more addresses associated with the neighboring memory cells from the memory device, and

refresh one or neighboring memory cells associated with the acquired one or more addresses.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072890/0340 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 11, 2013
From: RUBY, PAUL D.
To: INTEL CORPORATION
Reel/Frame 030588/0608 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2013
From: DAMLE, PRASHANT S.; HADY, FRANK T.; PANGAL, KIRAN; JAYACHANDRAN, SOWMIYA
To: INTEL CORPORATION
Reel/Frame 030059/0721 →
Continuity (1)
Related Publication 20140281203A1 · Sep 18, 2014