Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system

1. A system, comprising:

a controller comprising a plurality of first external terminals configured to supply a command and an address, to communicate data, and to communicate a strobe signal related to the data; and

a semiconductor memory device comprising a plurality of second external terminals corresponding to the plurality of first external terminals,

the semiconductor memory device further comprising a system clock external terminal provided to receive a system clock with a first frequency or a second frequency,

one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data, the length of the preamble including first and second lengths corresponding to the first and second frequencies, respectively.

2. The system as claimed in claim 1 , the device further comprising:

a data strobe signal output control circuit configured to output the preamble of the strobe signal and then output a toggle transition of the data strobe signal to communicate the data.

3. The system as claimed in claim 1 , wherein the more the frequency of the system clock is increased, the longer the length of the preamble is.

4. The system as claimed in claim 3 , wherein the larger a CAS latency is, the longer the length of the preamble is.

5. The system as claimed in claim 3 , wherein the length of the preamble is changed enough that the controller includes a gate opening area, which overlaps the length of the preamble, so that the controller can receive the data from the memory device.

6. The system as claimed in claim 1 , wherein the data strobe signal is transferred from the semiconductor memory device to the controller when performing a read operation.

7. The system as claimed in claim 1 , the controller further comprising:

a preamble length determination unit configured to determine the length of the preamble.

8. The system as claimed in claim 7 , wherein the preamble length determination unit determines the length of the preamble based on a variation of a delay time of the strobe signal.

9. The system as claimed in claim 7 , wherein the preamble length determination unit determines the length of the preamble for each of a fixed time interval.

10. A system, comprising:

a controller comprising a plurality of first external terminals configured to supply a command and an address, to communicate data, and to communicate a strobe signal related to the data; and

a plurality of semiconductor memory devices, each semiconductor memory device comprising a plurality of second external terminals corresponding to the plurality of first external terminals,

each of the semiconductor memory devices further comprising a system clock external terminal provided to receive a system clock with a first frequency or a second frequency,

one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data, the length of the preamble including first and second lengths corresponding to the first and second frequencies, respectively.

11. The system as claimed in claim 10 , wherein at least one of said plurality of semiconductor memory devices further comprises:

a delay locked loop (DLL) circuit; and

a DLL selection circuit that can select a DLL selection mode, which sets the DLL circuit in an activate mode, and a DLL non-selection mode, which sets the DLL circuit in a deactivate mode.

12. The system as claimed in claim 11 , wherein the length of the preamble is used to communicate data only during the deactivate mode.

13. The system as claimed in claim 10 , wherein the controller further comprises a preamble length determination unit that determines the length of the preamble.

14. The system as claimed in claim 13 , wherein the preamble length determination unit performs a data read test for the semiconductor memory device to determine the length of the preamble.

15. The system as claimed in claim 13 , wherein the preamble length determination unit determines the length of the preamble at a system start-up time.

16. The system as claimed in claim 13 , wherein the preamble length determination unit determines the length of the preamble for each of a fixed time interval.

17. The system as claimed in claim 13 , wherein the preamble length determination unit determines the length of the preamble based on a variation of a delay time of the strobe signal.

18. The system as claimed in claim 10 , wherein the preamble comprises a read preamble.

19. The system as claimed in claim 18 , wherein the data strobe signal is transferred from the semiconductor memory device to the controller when performing a read operation.

20. A method of communicating data to and from semiconductor memory devices,

for a controller comprising a plurality of first external terminals configured to supply a command and an address, to communicate data, and to communicate a strobe signal related to the data, and,

for a semiconductor memory device comprising a plurality of second external terminals corresponding to the plurality of first external terminals,

the semiconductor memory devices further comprising a system clock external terminal provided to receive a system clock with a first frequency or a second frequency, the method comprising

allocating one of the plurality of first external terminals and one of the plurality of second external terminals for transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data, the length of the preamble including first and second lengths corresponding to the first and second frequencies, respectively.