Retention detection and/or channel tracking policy in a flash memory based storage system
View Patent ↗A method for determining a retention time in a solid state device (SSD), comprising the steps of providing a plurality of write operations to a memory, determining a reference voltage for each of the write operations, determining a difference between (i) the reference voltage after each of the write operations and (ii) a target reference voltage and if the difference is above a predetermined value, generating a flag indicating an excessive retention has occurred.
1. A method for determining a retention time in a solid state drive (SSD), comprising the steps of:
programming a plurality of write operations to a memory;
tracking a reference voltage for each of said write operations;
detecting a difference between (i) said reference voltage determined after each of said write operations and (ii) an optimal reference voltage estimated for read operations from said memory after a pre-defined condition; and
if said difference is above a pre-defined threshold, initiating a policy to counteract retention effects.
2. The method according to claim 1 , further comprising the step of:
adjusting a channel tracking procedure in response to a raw bit error rate.
3. The method according to claim 1 , wherein said optimal voltage level is estimated after an erase operation.
4. The method according to claim 1 , wherein said method is invoked on an R-block level of said memory.
5. The method according to claim 1 , wherein said memory comprises a flash based memory.
6. The method according to claim 1 , wherein said method operates without invoking time or temperature calculations.
7. The method according to claim 1 , wherein said method is implemented with a channel tracking procedure of a controller of said solid state drive.
8. The method according to claim 7 , wherein said method is integrated on a digital signal processor of said controller.
9. The method according to claim 1 , wherein said policy comprises a retention policy operation.
10. An apparatus comprising:
a memory configured to process a plurality of write operations; and
a controller configured to (i) track a reference voltage for each of said write operations, (ii) detect a difference between (a) said reference voltage determined after each of said write operations and (b) an optimal reference voltage estimated for read operations from said memory after a pre-defined condition and (iii) if said difference is above a pre-defined threshold, initiate a policy to counteract retention effects.
11. The apparatus according to claim 10 , wherein a channel tracking procedure is adjusted in response to a raw bit error rate.
12. The apparatus according to claim 10 , wherein said controller is configured to track an R-block level of said memory.
13. The apparatus according to claim 10 , wherein said controller further comprises a digital signal processor implementing a channel tracking procedure.
14. The apparatus according to claim 10 , wherein said optimal voltage level is estimated after an erase operation.
15. The apparatus according to claim 10 , wherein said memory comprises a flash based memory.
16. The apparatus according to claim 10 , wherein said policy comprises a retention policy operation.
17. The method according to claim 1 , wherein said pre-defined condition is (i) a pre-defined program/erase cycle count in a first mode and (ii) a difference between (a) said reference voltage determined after each of said write operations and (b) a most recent reference voltage is greater than a threshold in a second mode.
18. The apparatus according to claim 10 , wherein said pre-defined condition is (i) a pre-defined program/erase cycle count in a first mode and (ii) a difference between (a) said reference voltage determined after each of said write operations and (b) a most recent reference voltage is greater than a threshold in a second mode.
19. The apparatus according to claim 10 , wherein said apparatus comprises a solid state drive (SSD).
20. An apparatus comprising:
an interface configured to process a plurality of write operations to a memory; and
a control circuit configured to (i) track a reference voltage for each of said write operations, (ii) detect a difference between (a) said reference voltage determined after each of said write operations and (b) an optimal reference voltage estimated for read operations from said memory after a pre-defined condition and (iii) if said difference is above a pre-defined threshold, initiate a policy to counteract retention effects.