IP Library Granted Patent US 8,981,477
Granted Patent B2
US 8,981,477 · App. 13/833,210 · Granted Mar 17, 2015

Laterally diffused metal oxide semiconductor

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,981,477
App. No.
13/833,210
Granted
Mar 17, 2015
Kind
B2
Abstract

A laterally-diffused metal oxide semiconductor (LDMOS) device and method of manufacturing the same are provided. The LDMOS device can include a drift region, a source region and a drain region spaced a predetermined interval apart from each other in the drift region, a field insulating layer formed in the drift region between the source region and the drain region, and a first P-TOP region formed under the field insulating layer. The LDMOS device can further include a gate polysilicon covering a portion of the field insulating layer, a gate electrode formed on the gate polysilicon, and a contact line penetrating the gate electrode, the gate polysilicon, and the field insulating layer.

Claims (14)

1. A laterally-diffused metal oxide semiconductor (LDMOS) device, comprising:

a drift region;

a source region and a drain region spaced a predetermined interval apart from each other in the drift region;

a field insulating layer formed in the drift region between the source region and the drain region;

a first P-TOP region formed under the field insulating layer;

a gate polysilicon covering a portion of the field insulating layer;

a gate electrode formed on the gate polysilicon;

a contact line penetrating the gate electrode, the gate polysilicon, and the field insulating layer; and

a high concentration second conductive first connection region formed in the first P-TOP region, wherein the high concentration second conductive first connection region is connected to a ground line to allow the first P-TOP region to be grounded.

2. The LDMOS device according to claim 1 , wherein the source region comprises a second P-TOP region into which a P-type high concentration impurity is ion-implanted.

3. The LDMOS device according to claim 1 , further comprising a ground line formed on the gate electrode.

4. The LDMOS device according to claim 1 , wherein the contact line is connected to an upper ground line.

5. The LDMOS device according to claim 1 , wherein the contact line comprises a plurality of continuous bar-type contact lines.

6. The LDMOS device according to claim 5 , wherein each of the bar-type contact lines comprises a plurality of hole types.

Assignments (2)
CHANGE OF NAME Recorded Nov 30, 2017
From: DONGBU HITEK CO., LTD.
To: DB HITEK CO., LTD.
Reel/Frame 044559/0819 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 4, 2013
From: MOON, NAM CHIL
To: DONGBU HITEK CO., LTD.
Reel/Frame 030150/0165 →