System and method for cycle slip correction
View Patent ↗A system and method including a parity bit encoder for encoding each n bits of data to be transmitted with a parity check bit to produce blocks of n+1 bits (n information bits plus one parity bit associated with the n information bits). Each of the blocks of n+1 bits are Gray mapped to a plurality of associated QAM symbols that are modulated onto an optical wavelength and transmitted to a receiver. A maximum a posteriori (MAP) decoder is used at the receiver to correct for cycle slip. Phase errors of 180 degrees may be detected by independently encoding odd and even bits prior to Gray mapping, and identifying errors in decoding odd numbered bits at the receiver.
1. A system comprising:
a parity bit encoder configured to encode successive blocks of n bits with a parity bit to provide successive blocks of n+1 bits;
a Gray mapper coupled to said parity bit encoder and configured to map each one of said blocks of n+1 bits to an associated plurality of quadrature amplitude modulated (QAM) symbols;
a modulator coupled to said Gray mapper and configured to modulate an optical signal in response to an output of said Gray mapper to provide a modulated optical signal comprising said associated plurality of QAM symbols;
a detector for receiving said modulated optical signal and providing an electrical signal representative of said optical signal; and
a de-mapper configured to provide a de-mapper output representative of said blocks of n bits in response to said electrical signal, said de-mapper being further configured to cause correction of cycle slip using parity indicated by said parity bit.
2. A system according to claim 1 , wherein said plurality of QAM symbols comprises an odd number of QAM symbols.
3. A system according to claim 1 , wherein said de-mapper is configured to provide said de-mapper output by selecting bits associated with a plurality of Gray mapped QAM symbols having a parity corresponding to said parity indicated by said parity bit and a minimum Euclidean distance from a received plurality of QAM symbols detected from said electrical signal.
4. A system according to claim 1 , said system further comprising
a demultiplexer configured to receive a serial input data stream and demultiplex said serial input data stream into a plurality of demultipexed data streams;
a plurality of forward error correction (FEC) encoders, each of said FEC encoders being configured to encode an associated one of said demultiplexed data streams using a FEC code and provide an associated FEC encoded output; and
an interleaver coupled said plurality of FEC encoders and configured to provide an interleaved output comprising said successive blocks of n bits to said parity bit encoder.
5. A system according to claim 1 , said system further comprising
a de-interleaver coupled to said de-mapper and configured to provide a plurality of de-interleaved outputs in response to said de-mapper output; and
a plurality of FEC decoders, each of said FEC decoders being configured to receive an associated one of said de-interleaved outputs and provide an associated FEC decoded output signal.
6. A system according to claim 5 , said system being configured to cause correction of 180 degree cycle slip in said carrier phase estimation in response to errors reported by ones of said FEC decoders associated with odd bits of said de-mapper output.
7. An optical signal receiver comprising:
a detector for receiving a modulated optical signal representing blocks of n+1 bits comprising n information bits and a parity bit mapped to an associated plurality of QAM signals and for providing an electrical signal representative of said optical signal; and
a de-mapper configured to provide a de-mapper output representative of said blocks of n bits in response to said electrical signal, said de-mapper being further configured to cause correction of cycle slip using parity indicated by said parity bit.
8. A receiver according to claim 7 , wherein said plurality of QAM symbols comprises an odd number of QAM symbols.
9. A receiver according to claim 7 , wherein said de-mapper is configured to provide said de-mapper output by selecting bits associated with a plurality of Gray mapped QAM symbols having a parity corresponding to said parity indicated by said parity bit and a minimum Euclidean distance from a received plurality of QAM symbols detected from said electrical signal.
10. A receiver according to claim 7 , said receiver further comprising
a de-interleaver coupled to said de-mapper and configured to provide a plurality of de-interleaved outputs in response to said de-mapper output; and
a plurality of FEC decoders, each of said FEC decoders being configured to receive an associated one of said de-interleaved outputs and provide an associated FEC decoded output signal.
11. A receiver according to claim 10 , said receiver being configured to cause correction of 180 degree cycle slip in said carrier phase estimation in response to errors reported by ones of said FEC decoders associated with odd bits of said de-mapper output.
12. A method comprising:
encoding successive blocks of n bits of a signal with a parity bit to provide successive blocks of n+1 bits;
Gray mapping said successive blocks of n+1 bits to an associated plurality of QAM symbols;
modulating said plurality of QAM symbols on an optical carrier wavelength to provide a modulated optical signal;
detecting said modulated optical signal to provide an electrical signal;
de-mapping said plurality of QAM symbols from said electrical signal to provide a de-mapper output representative of said blocks of n bits; and
using parity indicated by said parity bit to cause correction of cycle slip.
13. A method according to claim 12 , wherein said plurality of QAM symbols comprises an odd number of QAM symbols.
14. A method according to claim 12 , wherein said de-mapping comprises selecting bits associated with a plurality of Gray mapped QAM symbols having a parity corresponding to said parity indicated by said parity bit and a minimum Euclidean distance from a received plurality of QAM symbols detected from said electrical signal.
15. A method according to claim 12 , said method further comprising
demultiplexing an input signal to provide a plurality of demultiplexed data streams;
encoding each of said plurality of demultiplexed data streams using an forward error correction (FEC) code to provide a plurality of FEC encoded outputs; and
interleaving said FEC encoded outputs to provide said successive blocks of n bits.
16. A method according to claim 15 , said method further comprising
de-interleaving said de-mapper output to provide a plurality of de-interleaved outputs; and
decoding said de-interleaved outputs using said FEC code to provide a plurality of FEC decoded outputs.
17. A method according to claim 16 , said method further comprising identifying 180 degree cycle slip in said carrier phase estimation in response to ones of said FEC code decoded outputs corresponding to odd numbered bits of said de-mapper output.