VERTICAL LIGHT EMITTING DIODE AND MANUFACTURING METHOD AND APPLICATION THEREOF
A vertical light emitting diode (LED) is disclosed, which includes a conductive substrate; a conductive diamond-like carbon (DLC) layer located on the conductive substrate; a first passivation layer disposed on the conductive DLC layer and formed with a first opening; a first electrode located on the conductive DLC layer and in the first opening of the first passivation layer; a semiconductor epitaxial multilayer structure disposed on the first electrode; a second passivation layer disposed on the first passivation layer and covering the lateral surface of the semiconductor epitaxial multilayer structure, wherein a second opening is formed in the second passivation layer to expose the surface of the semiconductor epitaxial multilayer structure; and a second electrode located on the semiconductor epitaxial multilayer structure and in the second opening of the second passivation layer. A method for manufacturing the vertical LED mentioned above is also disclosed.
1 . A vertical light emitting diode, comprising:
a conductive substrate;
a conductive diamond-like carbon (DLC) layer located on the conductive substrate;
a first passivation layer disposed on the conductive DLC layer and formed with a first opening;
a first electrode located on the conductive DLC layer and in the first opening of the first passivation layer;
a semiconductor epitaxial multilayer structure disposed on the first electrode;
a second passivation layer disposed on the first passivation layer and covering the lateral surface of the semiconductor epitaxial multilayer structure, wherein a second opening is formed in the second passivation layer to expose the surface of the semiconductor epitaxial multilayer structure; and
a second electrode located on the semiconductor epitaxial multilayer structure and in the second opening of the second passivation layer.
2 . The vertical light emitting diode as claimed in claim 1 , wherein the first electrode includes a first electrode layer and a reflective layer, wherein the reflective layer is interposed between the first electrode layer and the semiconductor epitaxial multilayer structure.
3 . The vertical light emitting diode as claimed in claim 1 , wherein the semiconductor epitaxial multilayer structure includes a first semiconductor epitaxial layer, an active interlayer and a second semiconductor epitaxial layer, wherein the active interlayer is interposed between the first semiconductor epitaxial layer and the second semiconductor epitaxial layer.
4 . The vertical light emitting diode as claimed in claim 3 , wherein the first semiconductor epitaxial layer and the first electrode layer are each P type, and the second semiconductor epitaxial layer and the second electrode layer are each N type.
5 . The vertical light emitting diode as claimed in claim 3 , wherein the first electrode includes a first electrode layer and a reflective layer, wherein the reflective layer is interposed between the first electrode layer and the semiconductor epitaxial multilayer structure.
6 . The vertical light emitting diode as claimed in claim 1 , wherein the conductive DLC layer is a multilayer structure composed by a conductive material and a conductive DLC, a DLC layer including the conductive material, a graphitizing DLC layer or a combination thereof.
7 . The vertical light emitting diode as claimed in claim 1 , wherein the conductive substrate is composed of a metal, a ceramic including the conductive material or a diamond including the conductive material.
8 . The vertical light emitting diode as claimed in claim 1 , wherein the first passivation layer and the second passivation layer are each independently composed of silicon dioxide, silicon nitride, aluminum nitride, insulated DLC or a combination thereof.
9 . A method of manufacturing a vertical light emitting diode, comprising:
providing a temporary substrate and forming a semiconductor epitaxial multilayer structure, a first electrode and a first passivation layer on the temporary substrate, wherein the semiconductor epitaxial multilayer structure is disposed on the temporary substrate, the first passivation layer and the first electrode are disposed on the semiconductor epitaxial multilayer structure, the first passivation layer is patterned into a first opening, and the first electrode is embedded in the first opening of the first passivation layer;
forming a conductive DLC layer on the first passivation layer and the first electrode;
patterning the semiconductor epitaxial multilayer structure to expose the first passivation layer;
forming a second passivation layer on the patterned semiconductor epitaxial multilayer structure and the first passivation layer, wherein a plurality of second openings is disposed on the second passivation layer to expose the patterned semiconductor epitaxial multilayer structure; and
forming a second electrode in the second openings of the second passivation layer and on the patterned semiconductor epitaxial multilayer structure.
10 . The method as claimed in claim 9 , wherein the first passivation layer is formed on the semiconductor epitaxial multilayer structure and then patterned to form the first opening, after that, on the semiconductor epitaxial multilayer structure, forming the first electrode in the first opening of the first passivation layer.
11 . The method as claimed in claim 9 , before forming the second passivation layer, further comprising:
roughening the patterned semiconductor epitaxial multilayer structure.
12 . The method as claimed in claim 9 , wherein the first electrode includes a first electrode layer and a reflective layer, wherein the reflective layer is interposed between the first electrode layer and the semiconductor epitaxial multilayer structure.
13 . The method as claimed in claim 9 , wherein the semiconductor epitaxial multilayer structure includes a first semiconductor epitaxial layer, an active interlayer and a second semiconductor epitaxial layer, wherein the active interlayer is interposed between the first semiconductor epitaxial layer and the second semiconductor epitaxial layer.
14 . The vertical light emitting diode as claimed in claim 13 , wherein the first semiconductor epitaxial layer and the first electrode layer are each P type, and the second semiconductor epitaxial layer and the second electrode layer are each N type.
15 . The method as claimed in claim 13 , wherein the first electrode includes a first electrode layer and a reflective layer and the reflective layer is interposed between the first electrode layer and the semiconductor epitaxial multilayer structure.
16 . The method as claimed in claim 9 , wherein the conductive DLC layer is a multilayer structure composed by a conductive material and a conductive DLC, a DLC layer including the conductive material, a graphitizing DLC layer or a combination thereof.
17 . The method as claimed in claim 9 , wherein the conductive substrate is composed of a metal, a ceramic including the conductive material or a diamond including the conductive material.
18 . The method as claimed in claim 9 , wherein the first passivation layer and the second passivation layer is independently composed of silicon dioxide, silicon nitride, aluminum nitride, insulated DLC or a combination thereof.
19 . A chip on board (COB), comprising:
a print circuit board; and
a vertical light emitting diode as recited in claim 1 which is encapsulated in the print circuit board.
20 . The COB as claimed in claim 19 , wherein the print circuit board includes an insulated layer and a print circuit substrate, the insulated layer is at least one selected from the group consisting of diamond-like carbon, aluminum oxide, ceramic and an epoxy resin including diamond.
21 . The COB as claimed in claim 20 , wherein the print circuit substrate is a metal plate, a ceramic plate or a silicon substrate.