IP Library Granted Patent US 9,218,310
Granted Patent B2
US 9,218,310 · App. 13/835,000 · Granted Dec 22, 2015

Shared input/output (I/O) unit

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Quick Facts
Patent No.
US 9,218,310
App. No.
13/835,000
Granted
Dec 22, 2015
Kind
B2
Abstract

A system includes a bus, a processor operably coupled to the bus, a memory operably coupled to the bus, a plurality of input/output (I/O) devices operably coupled to the bus, where each of the I/O devices has a set of control registers, and a first shared I/O unit operably coupled to the bus. The first shared I/O unit has a plurality of shared functions and is configured to perform the shared functions, where the shared I/O functions are not included as functions on the I/O devices and the I/O devices and the processor interact with the first shared I/O unit to use one or more of the shared functions performed by the first shared I/O unit.

Claims (37)

1. A system, comprising:

a bus;

a processor operably coupled to the bus;

a memory operably coupled to the bus;

a plurality of input/output (I/O) devices operably coupled to the bus, each of the I/O devices having a set of control registers; and

a first shared I/O unit operably coupled to the bus, the first shared I/O unit having a plurality of shared functions and configured to perform the shared functions, wherein the shared I/O functions are not included as functions on the I/O devices and the I/O devices and the processor interact with the first shared I/O unit to use one or more of the shared functions performed by the first shared I/O unit.

2. The system of claim 1 wherein the first shared I/O unit is a part of the processor.

3. The system of claim 1 wherein the first shared I/O unit is a component separate from the processor.

4. The system of claim 1 wherein the plurality of shared functions comprises one or more interrupt controllers, one or more I/O memory management units (MMUs), a plurality of data queues and a plurality of connection state structures.

5. The system of claim 4 wherein the plurality of shared functions further comprises one or more remote direct memory access (RDMA) engines and one or more acceleration engines.

6. The system of claim 1 wherein the bus comprises an I/O interconnect bus.

7. The system of claim 1 wherein one of the I/O devices comprises an I/O interconnect bus.

8. The system of claim 1 wherein the plurality of devices operate as peers to the processor.

9. The system of claim 1 wherein the processor is a multiprocessor (MP) having at least two processors.

10. The system of claim 1 further comprising:

a second shared I/O unit operably coupled to the bus, the second shared I/O unit having a same plurality of shared functions as the first shared I/O unit and configured to perform the shared functions, wherein the shared I/O functions are not included as functions on the I/O devices and a first portion of the I/O devices and the processor interact with the first shared I/O unit to use one or more of the shared functions performed by the first shared I/O unit and a second portion of the I/O devices and the processor interact with the second shared I/O unit to use one or more of the shared functions performed by the second shared I/O unit.

11. A system, comprising:

a bus;

a multiprocessor having at least two processors, the multiprocessor operably coupled to the bus;

a memory operably coupled to the bus;

a plurality of input/output (I/O) devices operably coupled to the bus;

a first shared I/O unit operably coupled to the bus, the first shared I/O unit comprising a plurality of shared functions and configured to perform the shared functions, wherein the I/O devices and the multiprocessor interact with the first shared I/O unit to use one or more of the shared functions performed by the first shared I/O unit, the shared I/O functions including one or more interrupt controllers, one or more I/O memory management units (MMUs), and a plurality of data queues.

12. The system of claim 11 wherein the I/O devices include a set of control registers and do not include the shared I/O functions.

13. The system of claim 11 wherein the plurality of shared functions further comprises one or more remote direct memory access (RDMA) engines, one or more acceleration engines and a plurality of connection state structures.

14. The system of claim 11 wherein the bus comprises an I/O interconnect bus.

15. The system of claim 11 wherein the first shared I/O unit is a component separate from the multiprocessor.

16. The system of claim 11 further comprising:

a second shared I/O unit operably coupled to the bus, the second shared I/O unit having a same plurality of shared functions as the first shared I/O unit and configured to perform the shared functions, wherein:

a first portion of the I/O devices and a first processor of the multiprocessor interact with the first shared I/O unit to use one or more of the shared functions performed by the first shared I/O unit, and

a second portion of the I/O devices and a second processor of the multiprocessor interact with the second shared I/O unit to use one or more of the shared functions performed by the second shared I/O unit.

17. The system of claim 11 wherein each of the plurality of I/O devices operates as a peer to the multiprocessor.

18. The system of claim 11 wherein one of the plurality of I/O devices comprises a network interface device.

19. A method for performing input/output (I/O) operations among a plurality of I/O devices, the method comprising:

receiving data at a system, the system comprising a bus, a processor operably coupled to the bus, a plurality of I/O devices operably coupled to the bus and a shared I/O unit operably coupled to the bus, wherein the shared I/O unit includes a plurality of shared functions;

communicating the data between one or more of the I/O devices, the processor and the shared I/O device; and

performing one or more of the shared functions on the data by the shared I/O unit.

20. The method of claim 19 wherein the shared I/O functions are not included as functions on the I/O devices.

Assignments (2)
CHANGE OF NAME Recorded Oct 2, 2017
From: GOOGLE INC.
To: GOOGLE LLC
Reel/Frame 044566/0657 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2013
From: BARROSO, LUIZ ANDRE; LAUDON, JAMES
To: GOOGLE INC.
Reel/Frame 030728/0144 →