Isolated high voltage sampling network

1. A differential sampling circuit, comprising:

V DD and V SS voltage sources;

a differential input having a common mode voltage when a differential input signal is applied thereto;

a differential output for providing a sample of the differential input signal;

sampling circuitry coupled to the differential input and including a plurality of switches controlled to sample the differential input signal and store a replica of the common mode voltage at a common mode node, wherein the common mode voltage exceeds the voltages of the V DD and V SS sources; and

a logic control block powered by V DD and V SS sources and configured to control the switches.

2. The sampling circuit of claim 1 , wherein the differential output is AC coupled to the switches.

3. The sampling circuit of claim 1 , further comprising a respective series capacitor coupled between the logic control block and each switch, respectively.

4. The sampling circuit of claim 1 , further comprising an analog-to-digital converter (ADC) that is AC coupled to the differential output and configured to convert a voltage at the differential output into a digital signal.

5. The sampling circuit of claim 1 , further comprising a respective charge pump in series with a capacitor coupled between each switch and the logic control block, wherein each charge pump is configured to provide a gate to source voltage to its coupled switch sufficient to control an ON or OFF state of the switch.

6. The sampling circuit of claim 1 , further comprising a resistive divider connected between a positive input node and a negative input node of the differential input and configured to provide the replica of the common mode voltage to the common mode node.

7. A differential sampling circuit, comprising:

a differential input having a positive input node and a negative input node;

a differential output having a positive output node and a negative output node;

a first switch coupled between the negative input node and a negative internal storage node;

a second switch coupled between an internal common mode node and a negative internal storage node;

a third switch coupled between the internal common mode node and the positive internal storage node;

a fourth switch coupled between the positive input node and the positive internal storage node; and

a logic control block powered by V DD and V SS voltage sources and configured to control each switch so as to cause the differential sampling circuit to sample a common mode voltage at the differential input that exceeds the voltages of the V DD and V SS sources;

wherein the logic control block is AC coupled to:

the first switch via a first series capacitor;

the second switch via a second series capacitor;

the third switch via a third series capacitor; and

the fourth switch via a fourth series capacitor.

8. The sampling circuit of claim 7 , wherein the logic control block includes:

an input to receive a first clock; and

an input to receive a second clock.

9. The sampling circuit of claim 8 , wherein:

the first and fourth switches are configured to be ON when the first clock is high and the second clock is low; and

the second and third switches are configured to be OFF when the first clock is high and the second clock is low.

10. The sampling circuit of claim 7 , further comprising:

a first sampling capacitor connected in series between the positive internal storage node and the positive output node; and

a second sampling capacitor connected in series between the negative internal storage node and the negative output node.

11. The sampling circuit of claim 10 , further comprising an analog to digital circuit having:

a first input coupled to the positive output node; and

a second input coupled to the negative output node.

12. The sampling circuit of claim 7 , further comprising:

a first charge pump coupled between the first switch and the first series capacitor;

a second charge pump coupled between the second switch and the second series capacitor;

a third charge pump coupled between the third switch and the third series capacitor; and

a fourth charge pump coupled between the fourth switch and the fourth series capacitor.

13. The sampling circuit of claim 7 , further comprising a common mode storage capacitor coupled between the common mode node and ground.

14. The sampling circuit of claim 12 , wherein:

the first charge pump is configured to use a voltage of the negative input node of the differential input as a reference voltage to create a voltage sufficient to turn ON or OFF the first switch;

the second charge pump is configured to use a voltage of the internal common mode node as a reference voltage to create a voltage sufficient to turn ON or OFF the second switch;

the third charge pump is configured to use a voltage of the internal common mode node as a reference voltage to create a voltage sufficient to turn ON or OFF the third switch; and

the fourth charge pump is configured to use a voltage of the positive input node of the differential input as a reference voltage to create a voltage sufficient to turn ON or OFF the fourth switch.

15. The sampling circuit of claim 7 , wherein each switch is a metal-oxide-semiconductor field-effect transistor (MOSFET).

16. The sampling circuit of claim 15 , wherein:

the first charge pump comprises:

a first NFET having a source coupled to the negative node of the differential input; and

a second NFET having a source coupled to the negative node of the differential input;

wherein a gate of the first NFET and a gate of the second NFET are cross coupled;

the second charge pump comprises:

a first PFET having a source coupled to the internal common mode node; and

a second PFET having a source coupled to the internal common mode node; wherein a gate of the first and a gate of the second PFET are cross coupled;

the third charge pump comprises:

a third NFET having a source coupled to the internal common mode node; and

a fourth NFET having a source coupled to the internal common mode node; wherein a gate of the third NFET and a gate of the fourth NFET are cross coupled; and

the fourth charge pump comprises:

a second PFET having a source coupled to the positive node of the differential input; and

a third PFET having a source coupled to the positive node of the differential input;

wherein a gate of the second and a gate of the third PFET are cross coupled.

17. The sampling circuit of claim 15 , wherein each switch is configured to sample signals up to twice a maximum rated drain to source voltage.

18. In a differential sampling circuit, comprising:

a differential input having a positive input node and a negative input node;

a differential output having a positive output node and a negative output node;

a first switch coupled between the negative input node and a negative internal storage node;

a second switch coupled between an internal common mode node and the negative internal storage node;

a third switch coupled between the internal common mode node and the positive internal storage node;

a fourth switch coupled between the positive input node and the positive internal storage node;

at least one logic control block to control an ON or OFF state of each switch;

a method of sampling a differential signal comprising:

in a sample mode:

turn ON the first and fourth switch;

turn OFF the second and third switch;

store a voltage from the positive input node at the positive internal storage node (V CAPP ); and

store a voltage from the negative input node at the negative internal storage node (V CAPM );

in a charge transfer mode:

turn OFF the first and fourth switch;

turn ON the second and third switch;

store a voltage at the internal common mode (VCM) node based on:

VCM

=

V

CAPP

+

V

CAPM

2

;

wherein each switch is controlled by the logic control block via AC coupling.

19. The method of claim 18 , further comprising powering the logic control block by power supply levels V DD and a V SS , wherein the voltage stored at the internal common mode node is ≧(V DD −V SS ).

20. The method of claim 18 , wherein, in the sample mode, a voltage across each switch is up to twice a maximum rated drain to source voltage of each switch, respectively.

21. The method of claim 18 , wherein:

turning ON the first switch comprises using the voltage at the negative input node as a reference to pump up to a voltage level that exceeds a gate to source voltage of the first switch;

turning ON the second switch comprises using the voltage at the internal common mode node as a reference to pump up to a voltage level that exceeds a gate to source voltage of the second switch;

turning ON the third switch comprises using the voltage at the internal common mode node as a reference to pump up to a voltage level that exceeds a gate to source voltage of the third switch; and

turning ON the fourth switch comprises using the voltage at the positive input node as a reference to pump up to a voltage level that exceeds a gate to source voltage of the fourth switch.

22. The method of claim 18 , further comprising:

AC coupling the positive internal storage node with the positive output node; and

AC coupling the negative internal storage node with the negative output node.

23. The method of claim 18 , wherein the sample mode further comprises floating the internal common mode node.

24. The method of claim 18 , further comprising:

powering the logic control block with VDD and VSS voltage sources; and

receiving a common mode voltage at the differential input that exceeds in magnitude at least one of:

(i) the VDD voltage source; and

(ii) the VSS voltage source.