Disclosed herein is a gate driver. The gate driver according to an exemplary embodiment of the present invention includes: a first power switch sourcing current according to voltage applied by a voltage source; a second power switch connected with the first power switch in series and sinking current according to the voltage applied by the voltage source; and a speed booster receiving a voltage pulse from the outside to output peak current so as to make a turn on/off operation of the first power switch fast. As set forth above, according to the exemplary embodiments of the present invention, it is possible to improve the driving speed of the gate driver without increasing the current of the current source by further including the speed booster configured of the plurality of MOSFETs and the capacitor.
1. A gate driver, comprising:
a first power switch sourcing current according to voltage applied by a voltage source;
a second power switch connected with the first power switch in series and sinking current according to the voltage applied by the voltage source;
a speed booster outputting peak current so as to make a turn on/off operation of the first power switch fast; and
an amplifier amplifying current flowing in the first power switch side,
wherein the speed booster is configured of a serial-parallel combination circuit of a plurality of MOSFETs and one capacitor.
2. The gate driver according to claim 1 , further comprising:
an inverter unit outputting a signal for driving the first and second power switches.
3. The gate driver according to claim 1 , further comprising:
a level shifter shifting a voltage level to drive the first power switch.
4. The gate driver according to claim 3 , wherein the level shifter includes first and second NMOSs that are a parallel connection relationship with each other.
5. The gate driver according to claim 4 , wherein the speed booster is configured of a serial-parallel combination circuit of four MOSFETs and one capacitor.
6. The gate driver according to claim 5 , wherein the speed booster is configured to have a structure in which four NMOSs are disposed at each of the squared vertex portions so that first and third NMOSs and second and fourth NMOSs form each a diagonal to each other, gates of the first and third NMOSs are connected with an input terminal of the level shifter, gates of the second and fourth NMOSs are connected with an output terminal of the level shifter, a source of the first NMOS and a drain of the fourth NMOS are connected with each other, a source of the second NMOS and a drain of the third NMOS are connected With each other, drains of the first and second NMOSs are each connected with drains of the first and second NMOS of the level shifter, a source of the third and fourth NMOSs are each connected with a ground, and the capacitor is installed between a first common node N 1 at which the source of the first NMOS and the drain of the fourth NMOS are connected with each other and a second common node N 2 at which the source of the second NMOS and the drain of the third NMOS are connected with each other.