Active matrix emissive micro LED display
A display panel and a method of forming a display panel are described. The display panel may include a thin film transistor substrate including a pixel area and a non-pixel area. The pixel area includes an array of bank openings and an array of bottom electrodes within the array of bank openings. An array of micro LED devices are bonded to the corresponding array of bottom electrodes within the array of bank openings. An array of top electrode layers are formed electrically connecting the array of micro LED devices to a ground line in the non-pixel area.
1. An active matrix display panel comprising:
a thin film transistor (TFT) substrate including a pixel area and a non-pixel area, wherein the pixel area includes an array of bank openings and an array of bottom electrodes within the array of bank openings;
a ground line in the non-pixel area;
an array of micro LED devices on the array of bottom electrodes within the corresponding array of bank openings; and
an array of top electrode layers electrically connecting the array of micro LED devices to the ground line;
wherein each micro LED device is a vertical micro LED device with a maximum width of 1 μm-100 μm.
2. The display panel of claim 1 , wherein the ground line is a ground ring in the non-pixel area around the pixel area.
3. The display panel of claim 2 , wherein the array of top electrode layers are electrically connected to the ground ring on opposite sides of the pixel area.
4. The display panel of claim 3 , wherein each top electrode layer spans over a single row of micro LED devices.
5. The display panel of claim 3 , wherein each top electrode layer spans over a plurality of rows of micro LED devices.
6. The display panel of claim 1 , wherein the pixel area is not completely covered by the array of top electrode layers.
7. The display panel of claim 1 , wherein the array of bottom electrodes are formed on sidewalls of the corresponding array of bank openings.
8. The display panel of claim 7 , wherein the array of bottom electrodes are reflective to the visible wavelength range.
9. The display panel of claim 1 , further comprising a patterned insulator layer covering the array of bottom electrodes, and an array of openings in the patterned insulator layer exposing the array of bottom electrodes.
10. The display panel of claim 9 , wherein the patterned insulator layer covers edges of the array of bottom electrodes.
11. The display panel of claim 1 , further comprising a transparent passivation layer spanning sidewalls of the array of micro LED devices within the array of bank openings, wherein the transparent passivation layer does not completely cover a top conductive contact of each micro LED device.
12. The display panel of claim 1 , wherein the array of top electrode layers are formed of a transparent or semi-transparent material.
13. The display panel of claim 12 , wherein the array of top electrode layers comprise a material selected from the group consisting of PEDOT and ITO.
14. The display panel of claim 1 , wherein each vertical micro LED device comprises an inorganic semiconductor-based p-n diode.
15. The display panel of claim 14 , wherein each vertical micro LED device includes a corresponding bottom conductive contact with a maximum width of 1 μm-100 μm.
16. The display panel of claim 15 , wherein the corresponding bottom conductive contact of each vertical micro LED device is bonded to a corresponding bottom electrode.
17. The display panel of claim 16 , wherein each bottom electrode is independently addressable.
18. The display panel of claim 16 , wherein each vertical micro LED device has a maximum width of 1 μm-20 μm.