Power line communication device that is resilient to cross-band interference

1. An apparatus, comprising:

a power line communication (PLC) device that is configured to communicate on alternating current (AC) power wiring in a frequency range of 9 kilohertz to 500 kilohertz and does not use automatic gain control (AGC) functionality prior to analog to digital conversion, the PLC device including:

an over-sampled analog-to-digital converter (ADC) with a sample clock of at least 10 megahertz and includes:

a loop filter that maintains a noise power spectral density that does not exceed 3 decibels above a minimum noise floor, of the noise power spectral density, at 80 kilohertz or above, and

a digital filter and decimator configured to remove quantization noise, wherein a decimation factor of the decimator is such that it provides an output decimation rate between 350 kilohertz and 1.6 megahertz.

2. The apparatus of claim 1 , wherein the PLC device further includes:

a digital signal processing (DSP) processor coupled with an output of the over-sampled ADC, wherein the DSP processor has a 17 to 28 input bit width.

3. The apparatus of claim 1 , wherein the PLC device is compliant with one or more of the following standards:

European Committee for Electrotechnical Standardization (CENELEC) standard EN 50065-1;

International Telecommunication Union Telecommunication Standardization Sector (ITU-T) G.9902;

ITU-T G.9903;

ITU-T G.9904;

International Organization for Standardization/International Electrotechnical Commission (ISO/IEC) 14908-3; and

Institute of Electrical and Electronics Engineers (IEEE) P1901.2/D0.07.00.

4. The apparatus of claim 1 , wherein the over-sampled ADC includes a sigma-delta modulator.

5. The apparatus of claim 4 , wherein the sigma-delta modulator is a multi-stage noise shaping (MASH) structure.

6. The apparatus of claim 4 , wherein the sigma-delta modulator is a 3 rd order sigma-delta modulator.

7. The apparatus of claim 1 , wherein the decimation factor is programmable.

8. The apparatus of claim 1 , wherein the PLC device further includes:

a high-pass filter configured to remove AC mains voltage; and

a low-pass filter configured to prevent aliasing.

9. A method in a power line communications (PLC) receiver that communicates on alternating current (AC) power wiring in a frequency range of 9 kilohertz to 500 kilohertz, comprising:

receiving an analog signal at the PLC receiver, wherein the PLC receiver does not use an automatically adjusted gain function prior to analog-to-digital conversion;

processing the analog signal at an over-sampled analog-to-digital converter (ADC) with a sample clock of at least 10 megahertz, wherein the over-sampled ADC uses a loop filter that maintains a noise power spectral density that does not exceed 3 decibels above a minimum noise floor, of the noise power spectral density, at 80 kilohertz or above; and

removing quantization noise using a digital filter and decimator, wherein a decimation factor of the decimator is such that it provides an output decimation rate between 350 kilohertz and 1.6 megahertz.

10. The method of claim 9 , further comprising:

processing the output of the digital filter and decimator at a digital signal processor that is coupled to the over-sampled ADC, wherein the digital signal processor has a 17 to 28 input bit width.

11. The method of claim 9 , wherein the PLC device is compliant with one or more of the following standards:

European Committee for Electrotechnical Standardization (CENELEC) standard EN 50065-1;

International Telecommunication Union Telecommunication Standardization Sector (ITU-T) G.9902;

ITU-T G.9903;

ITU-T G.9904;

International Organization for Standardization/International Electrotechnical Commission (ISO/IEC) 14908-3; and

Institute of Electrical and Electronics Engineers (IEEE) P1901.2/D0.07.00.

12. The method of claim 9 , wherein the over-sampled ADC includes a sigma-delta modulator.

13. The method of claim 12 , wherein the sigma-delta modulator is a multi-stage noise shaping (MASH) structure.

14. The method of claim 12 , wherein the sigma-delta modulator is a 3 rd order sigma-delta modulator.

15. The method of claim 9 , wherein the decimation factor is programmable.

16. The method of claim 9 , further comprising:

prior to processing the analog signal at the over-sampled ADC, performing the following:

removing AC mains voltage from the analog signal using a high-pass filter, and

preventing aliasing using a low-pass filter.

17. An apparatus, comprising:

a power line communication (PLC) device that is configured to communicate on alternating current (AC) power wiring in a frequency range of 9kilohertz to 500 kilohertz and does not use automatic gain control (AGC) functionality prior to analog to digital conversion, the PLC device including:

an over-sampled analog-to-digital converter (ADC) with a sample clock of at least 10 megahertz and includes:

a sigma-delta modulator that has a loop filter that maintains a noise power spectral density that does not exceed 3 decibels above a minimum noise floor, of the noise power spectral density, at 80 kilohertz or above, and

a digital filter and decimator configured to remove quantization noise,

wherein a decimation factor of the decimator is such that it provides an output decimation rate between 350 kilohertz and 1.6 megahertz; and

wherein the PLC device is compliant with one or more of the following standards:

European Committee for Electrotechnical Standardization (CENELEC) standard EN 50065-1,

International Telecommunication Union Telecommunication Standardization Sector (ITU-T) G.9902,

ITU-T G.9903,

ITU-T G.9904,

International Organization for Standardization/International Electrotechnical Commission (ISO/IEC) 14908-3, and

Institute of Electrical and Electronics Engineers (IEEE) P1901.2/D0.07.00.

18. The apparatus of claim 17 , wherein the sigma-delta modulator is a multi-stage noise shaping (MASH) structure.

19. The apparatus of claim 17 , wherein the sigma-delta modulator is a 3 rd order sigma-delta modulator.

20. The apparatus of claim 17 , wherein the decimation factor is programmable.