IP Library Granted Patent US 9,118,584
Granted Patent B2
US 9,118,584 · App. 13/844,181 · Granted Aug 25, 2015

Dynamic scalable baseboard management controller stacks on single hardware structure

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,118,584
App. No.
13/844,181
Granted
Aug 25, 2015
Kind
B2
Abstract

Certain aspects of the present disclosure are directed to a baseboard management controller (BMC) managing a computer system including N computer nodes and N is an integer greater than 1. The BMC has: (a) a processor, (b) a first communication interface controller, (c) a memory. The memory stores a firmware, and the firmware is executed by a processor of the BMC. The firmware, when executed by the processor, is configured to (a) dynamically obtain the value of N, and (b) initiate N virtual BMC stacks each managing at least one health or performance related aspect of a respective one of the N computer nodes. The first and second virtual BMC stacks of the N virtual BMC stacks communicate, through the first communication interface controller, with the first and second computer nodes of the N computer nodes, respectively.

Claims (44)

1. A baseboard management controller (BMC) managing a computer system including N computer nodes, N being an integer greater than 1, comprising:

a processor;

a first communication interface controller;

a memory having firmware stored therein, wherein the firmware, when executed by the processor, is configured to

dynamically obtain the value of N; and

initiate N virtual BMC stacks each managing at least one health or performance related aspect of a respective one of the N computer nodes, wherein first and second virtual BMC stacks of the N virtual BMC stacks communicate, through the first communication interface controller, with the first and second computer nodes of the N computer nodes, respectively.

2. The BMC of claim 1 , wherein the firmware, when executed by the processor, is configured to access a configuration file to obtain the value of N.

3. The BMC of claim 1 , wherein the firmware, when executed by the processor, is configured to

initiate a predetermined number of virtual BMC stacks, including the first virtual BMC stack, during a booting process, wherein the first virtual BMC stack communicates with each of the N computer nodes to obtain the value of N.

4. The BMC of claim 3 , wherein the first virtual BMC stack is configured to receive an IPMI message from each of the N computer notes during obtaining the value of N.

5. The BMC of claim 4 , wherein the first virtual BMC stack is configured to receive the IPMI message from a BIOS or an OS of the each computer node.

6. The BMC of claim 1 , wherein the firmware, when executed by the processor, is configured to

initiate a predetermined number of virtual BMC stacks, including the first virtual BMC stack, during a booting process, wherein the first virtual BMC stack receives an IPMI message from one of the N computer nodes, the IPMI message indicating the value of N.

7. The BMC of claim 1 , wherein each of the virtual BMC stacks implements all management functions for managing health and performance related aspects of the respective one of the N computer nodes.

8. The BMC of claim 1 , wherein each of the virtual BMC stacks includes a Web server, a management program, a redirection program, and a virtual media program.

9. The BMC of claim 1 , wherein the first communication interface controller is a controller for controlling one of a keyboard controller style (“KCS”) interface, a system management interface chip (“SMIC”) interface, a block transfer (“BT”) interface, an SMBus System Interface (SSIF), an IPMB interface, a USB interface, a serial/modem interface, and a network interface.

10. The BMC of claim 1 , further comprising a second communication interface controller different from the first communication interface controller, wherein the first and second virtual BMC stacks communicate, through the second communication interface controller, with the first and second computer nodes, respectively.

11. A base board management controller (BMC) implemented method for managing a computer system having N computer nodes, N being an integer greater than 1, comprising:

dynamically obtaining, at the BMC, the value of N by accessing a configuration file by a firmware stored in a memory of the BMC; and

initiating N virtual BMC stacks at a processor, each managing at least one health or performance related aspect of a respective one of the N computer nodes, wherein first and second virtual BMC stacks of the N virtual BMC stacks communicate, through a first communication interface controller, with the first and second computer nodes of the N computer nodes, respectively.

12. The BMC implemented method of claim 11 , comprising:

initiating, at the BMC, a predetermined number of virtual BMC stacks, including the first virtual BMC stack, during a booting process, wherein the first virtual BMC stack communicates with each of the N computer nodes to obtain the value of N.

13. The BMC implemented method of claim 12 , further comprising:

receiving, at the first virtual BMC stack, an IPMI message from each of the N computer notes during obtaining the value of N; and

receiving, at the first virtual BMC stack, the IPMI message from a BIOS or an OS of the each computer node.

14. The BMC implemented method of claim 11 , further comprising:

initiating, at the BMC, a predetermined number of virtual BMC stacks, including the first virtual BMC stack, during a booting process, wherein the first virtual BMC stack receives an IPMI message from one of the N computer nodes, the IPMI message indicating the value of N.

15. The BMC implemented method of claim 11 , wherein each of the virtual BMC stacks implements all management functions for managing health and performance related aspects of the respective one of the N computer nodes.

16. The BMC implemented method of claim 11 , wherein each of the virtual BMC stacks includes a Web server, a management program, a redirection program, and a virtual media program.

17. The BMC implemented method of claim 11 , wherein the first communication interface controller is a controller for controlling one of a keyboard controller style (“KCS”) interface, a system management interface chip (“SMIC”) interface, a block transfer (“BT”) interface, an SMBus System Interface (SSIF), an IPMB interface, a USB interface, a serial/modem interface, and a network interface.

18. The BMC implemented method of claim 11 , further comprising: the first and second virtual BMC stacks communicating, through a second communication interface controller, with the first and second computer nodes, respectively, wherein the second communication interface controller is different from the first communication interface controller.

19. A non-transitory computer storage medium having computer-executable instructions stored thereon which, when executed by a processor of a base board management controller (BMC), cause the processor to:

dynamically obtain a value of N, N being an integer greater than 1; and

initiate N virtual BMC stacks at the processor, each managing at least one health or performance related aspect of a respective one of the N computer nodes, wherein first and second virtual BMC stacks of the N virtual BMC stacks communicate, through a first communication interface controller, with the first and second computer nodes of the N computer nodes, respectively.

20. The non-transitory computer storage medium of claim 19 , wherein the computer-executable instructions cause the processor to

initiate, at the BMC, a predetermined number of virtual BMC stacks, including the first virtual BMC stack, during a booting process, wherein the first virtual BMC stack communicates with each of the N computer nodes to obtain the value of N.

21. The non-transitory computer storage medium of claim 19 , wherein the computer-executable instructions cause the processor to

receive, at the first virtual BMC stack, an IPMI message from each of the N computer notes during obtaining the value of N; and

receive, at the first virtual BMC stack, the IPMI message from a BIOS or an OS of the each computer node.

22. The non-transitory computer storage medium of claim 19 , wherein the computer-executable instructions cause the processor to

initiate, at the BMC, a predetermined number of virtual BMC stacks, including the first virtual BMC stack, during a booting process, wherein the first virtual BMC stack receives an IPMI message from one of the N computer nodes, the IPMI message indicating the value of N.

23. The non-transitory computer storage medium of claim 19 , wherein each of the virtual BMC stacks implements all management functions for managing health and performance related aspects of the respective one of the N computer nodes, and each of the virtual BMC stacks includes a Web server, a management program, a redirection program, and a virtual media program.

24. The non-transitory computer storage medium of claim 19 , wherein the first communication interface controller is a controller for controlling one of a keyboard controller style (“KCS”) interface, a system management interface chip (“SMIC”) interface, a block transfer (“BT”) interface, an SMBus System Interface (SSIF), an IPMB interface, a USB interface, a serial/modem interface, and a network interface.

25. The non-transitory computer storage medium of claim 19 , wherein the computer-executable instructions cause the processor to communicate the first and second virtual BMC stacks, through a second communication interface controller, with the first and second computer nodes, respectively, wherein the second communication interface controller is different from the first communication interface controller.

Assignments (5)
PATENT SECURITY AGREEMENT Recorded Oct 23, 2024
From: AMERICAN MEGATRENDS INTERNATIONAL, LLC
To: BAIN CAPITAL CREDIT, LP, AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
Reel/Frame 069229/0834 →
RELEASE OF SECURITY INTEREST Recorded Oct 17, 2024
From: MIDCAP FINANCIAL TRUST
To: AMERICAN MEGATRENDS INTERNATIONAL, LLC
Reel/Frame 069205/0795 →
SECURITY INTEREST Recorded May 6, 2019
From: AMERICAN MEGATRENDS INTERNATIONAL, LLC
To: MIDCAP FINANCIAL TRUST, AS COLLATERAL AGENT
Reel/Frame 049087/0266 →
ENTITY CONVERSION Recorded Apr 15, 2019
From: AMERICAN MEGATRENDS, INC.
To: AMERICAN MEGATRENDS INTERNATIONAL, LLC
Reel/Frame 049091/0973 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2013
From: CHRISTOPHER, SAMVINESH; AYANAM, VARADACHARI SUDAN
To: AMERICAN MEGATRENDS, INC.
Reel/Frame 030023/0596 →