Semiconductor memory, memory system, and operation method thereof

1. A memory system, comprising:

a semiconductor memory including a storage unit configured to store a parameter information in response to a test mode signal and to output the stored parameter information in response to a parameter request signal; and

a memory controller configured to provide the parameter request signal to the semiconductor memory and receive the parameter information from the semiconductor memory device,

wherein the parameter information corresponds to a skew between the data strobe signal and the system clock.

2. The memory system of claim 1 , wherein the semiconductor memory further includes a delay locked loop configured to generate a data strobe signal based on a system clock.

3. The semiconductor memory of claim 1 , wherein the parameter information is generated in response to a request signal form the memory controller and is output through a power-up sequence in the normal operation.

4. The memory system of claim 1 , wherein the storage unit comprises a register configured to store the parameter information in test mode.

5. The memory system of claim 1 , wherein the storage unit comprises a register circuit or a fuse circuit.

6. The memory system of claim 1 , wherein the parameter information is output as a binary number form or a period information form.

7. The memory system of claim 1 , wherein the parameter information is a clock-based signal.

8. A semiconductor memory, comprising:

a delay locked loop configured to generate a data strobe signal based on a system clock; and

a storage unit configured to store a parameter information in a test operation and to output the stored parameter information in a normal operation,

wherein the parameter information corresponds to a skew between the data strobe signal and the system clock.

9. The semiconductor memory of claim 8 , wherein the storage unit outputs the stored parameter information in response to a parameter request signal received from a memory controller.

10. The semiconductor memory of claim 8 , wherein the stored parameter information is output through a power-up sequence in the normal operation.

11. The semiconductor memory of claim 9 , wherein the stored parameter information is output as a binary number form or a period information form.

12. The semiconductor memory of claim 8 , wherein the storage unit comprises a register circuit or a fuse circuit.

13. An operation method of a memory controller, the method comprising:

requesting a parameter information to a semiconductor memory, wherein the parameter information is stored in a test operation for the semiconductor memory;

receiving the parameter information output from the semiconductor memory; and

setting a parameter value for the semiconductor memory based on the parameter information,

wherein the parameter information corresponds to a skew between the data strobe signal and the system clock.

14. The operation method of claim 13 , wherein the parameter value is an interface value.

15. The operation method of claim 13 , wherein the semiconductor memory configured to generate and output a data strobe signal based on a system clock.

16. The operation method of claim 13 , wherein the parameter information is output in a power-up sequence of the semiconductor memory.

17. The operation method of claim 13 , wherein, in the receiving of the parameter information, the parameter information is output as a binary number form or a period information form.

18. The operation method of claim 13 , wherein the parameter information is a clock-based signal.