SEMICONDUCTOR DEVICE HAVING PLURAL CHIP CONNECTED TO EACH OTHER
Disclosed herein is a device that includes: a first timing adjustment circuit generating a first control signal based on a command and an output buffer outputting a plurality of data sets in a serial at a timing based on the first control signal; and a second semiconductor chip including: a plurality of holding circuits holding the data sets in parallel, a second timing adjustment circuit generating a second control signal based on the command, and an input buffer sequentially capturing the data sets supplied from the holding circuits based on the second control signal.
1 . A semiconductor device comprising:
a first semiconductor chip including:
a first timing adjustment circuit generating a first control signal based on a command; and
an output buffer outputting a plurality of data sets in a serial at a timing based on the first control signal; and
a second semiconductor chip including:
a plurality of holding circuits holding the data sets in parallel;
a second timing adjustment circuit generating a second control signal based on the command; and
an input buffer sequentially capturing the data sets supplied from the holding circuits based on the second control signal.
2 . The semiconductor device as claimed in claim 1 , wherein
the second semiconductor chip is a core chip including a memory cell array,
the first semiconductor chip is an interface chip controlling the core chip, and
the data sets are write data sets that are to be written into the memory cell array via the interface chip.
3 . The semiconductor device as claimed in claim 1 , wherein the second semiconductor chip further includes a delay adjustment circuit that adjusts a timing at which the second control signal is generated.
4 . The semiconductor device as claimed in claim 3 , wherein one of the first and second semiconductor chips further includes a storage circuit in which a delay amount of the delay adjustment circuit is stored.
5 . The semiconductor device as claimed in claim 4 , wherein the delay amount stored in the storage circuit is adjustable by a control signal supplied from outside.
6 . The semiconductor device as claimed in claim 3 , wherein the second semiconductor chip further includes a determination circuit that determining the data sets output from the input buffer.
7 . The semiconductor device as claimed in claim 3 , wherein the storage circuit includes a nonvolatile storage element.
8 . The semiconductor device as claimed in claim 1 , wherein the second semiconductor chip further includes:
a second timing adjustment circuit generating a third control signal that represents a timing at which the data sets are output from the first semiconductor chip in response to the command; and
an output circuit outputting the data sets based on the third control signal.
9 . The semiconductor device as claimed in claim 1 , wherein the first semiconductor chip and the second semiconductor chip are connected via a plurality of signal paths including penetrating electrodes that penetrating through at least one of the first and second semiconductor chips.
10 . A semiconductor device comprising:
a first semiconductor chip including:
a holding circuit having a data input node, the holding circuit capturing and temporarily holding data appearing on the data input node in response to a first timing signal;
a buffer circuit coupled to the holding circuit, the buffer circuit outputting the data held by the holding circuit in response to a second timing signal;
a first timing circuit generating one of the first and second timing signals;
a second semiconductor chip includes a second timing circuit generating the other one of the first and second timing signals; and
a latch circuit holding a control data that are used to adjust a gap between a timing at which the first timing signal is brought to an active level and a timing at which the second timing signal is brought to an active level.
11 . The semiconductor device as claimed in claim 10 , wherein the holding circuit comprises a FIFO circuit that captures data in accordance with the first timing signal.
12 . The semiconductor device as claimed in claim 10 , wherein the latch circuit is provided in the second semiconductor chip.
13 . The semiconductor device as claimed in claim 10 , wherein the first semiconductor chip is stacked on the second semiconductor chip.
14 . The semiconductor device as claimed in claim 10 , further comprising a penetrating electrode provided on at least one of the first and second semiconductor chips.
15 . The semiconductor device as claimed in claim 10 , wherein
the first semiconductor chip is a core chip including a memory cell array, and
the second semiconductor chip is an interface chip controlling the core chip.
16 . A semiconductor device comprising:
a first chip including a FIFO circuit connected to an input node thereof; and
a second chip supplying an input data to the input node of the FIFO circuit,
wherein the first and second chips are stacked to each other.
17 . The semiconductor device as claimed in claim 16 , further comprising a plurality of penetrating electrodes provided on at least one of the first and second chips,
wherein the input node is connected to at least one of the penetrating electrodes.
18 . The semiconductor device as claimed in claim 16 , wherein the FIFO circuit captures the input data in response to a first timing signal generated by the second chip.
19 . The semiconductor device as claimed in claim 16 , wherein the first chip further includes a buffer circuit connected to an output node of the FIFO circuit, the buffer circuit outputs data held by the FIFO circuit in response to a second timing signal generated by the first chip.
20 . The semiconductor device as claimed in claim 16 , wherein the first chip further includes another FIFO circuit connected to the input node, the another FIFO circuit is activated when outputting an output data to the second chip via the input node.