IP Library › Patent Application 13846730
Patent Application
App. No. 13/846,730

Semiconductor Device

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Quick Facts
Patent No.
US None
App. No.
13/846,730
Abstract

To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.

Claims (64)

1 - 19 . (canceled)

20 . A semiconductor chip comprising:

a semiconductor chip having an obverse surface over which a first electrode pad is formed and a reverse surface opposite the obverse surface;

a die pad over which the semiconductor chip is mounted;

a first lead electrically connected to the semiconductor chip; and

an Al ribbon electrically connected to the first electrode pad of the semiconductor chip and the first lead;

a sealing body sealing the semiconductor chip, a part of the first lead, and the Al ribbon,

wherein the semiconductor chip is mounted over the die pad via an Ag paste such that the reverse surface of the semiconductor chip faces to the die pad, and

wherein a portion of the die pad which the Ag paste contacts is an Ag plated layer.

21 . The semiconductor device according to claim 20 ,

wherein a second electrode pad is formed over the obverse surface of the semiconductor chip,

wherein a second lead is electrically connected to the semiconductor chip,

wherein an Au wire is electrically connected to the second electrode pad of the semiconductor chip and the second lead, and

wherein a portion of the second lead to which the Au wire is electrically connected is the Ag plated layer.

22 . The semiconductor device according to claim 20 ,

wherein the first lead is formed by Cu, and

wherein a portion of the first lead to which the Al ribbon is electrically connected is not a plated layer.

23 . The semiconductor device according to claim 20 ,

wherein the semiconductor chip includes a trench gate power MOSFET, and

wherein the first electrode pad of the semiconductor chip is a source electrode pad.

24 . The semiconductor device according to claim 20 ,

wherein the semiconductor chip includes an insulated gate bipolar transistor, and

wherein the first electrode pad of the semiconductor chip is an emitter electrode pad.

25 . The semiconductor device according to claim 21 ,

wherein the semiconductor chip includes a trench gate power MOSFET, and

wherein the first electrode pad of the semiconductor chip is a source electrode pad and the second electrode pad of the semiconductor chip is a gate electrode pad.

26 . The semiconductor device according to claim 25 ,

wherein an area of the first electrode pad of the semiconductor chip is larger than an area of the second electrode pad of the semiconductor chip.

27 . The semiconductor device according to claim 21 ,

wherein the semiconductor chip includes an insulated gate bipolar transistor, and

wherein the first electrode pad of the semiconductor chip is an emitter electrode pad and the second electrode pad of the semiconductor chip is a gate electrode pad.

28 . The semiconductor device according to claim 27 ,

wherein an area of the first electrode pad of the semiconductor chip is larger than an area of the second electrode pad of the semiconductor chip.

29 . A semiconductor chip comprising:

a semiconductor chip having an obverse surface over which a first electrode pad is formed and a reverse surface opposite the obverse surface;

a die pad over which the semiconductor chip is mounted;

a first lead electrically connected to the semiconductor chip;

an Al ribbon electrically connected to the first electrode pad of the semiconductor chip and the first lead; and

a sealing body sealing the semiconductor chip, a part of the first lead, and the Al ribbon,

wherein the semiconductor chip is mounted over the die pad via an Ag paste such that the reverse surface of the semiconductor chip faces to the die pad, and

wherein a portion of the die pad which the Ag paste contacts is a Pd plated layer.

30 . The semiconductor device according to claim 29 ,

wherein a second electrode pad is formed over the obverse surface of the semiconductor chip,

wherein a second lead is electrically connected to the semiconductor chip,

wherein an Au wire is electrically connected to the second electrode pad of the semiconductor chip and the second lead, and

wherein a portion of the second lead to which the Au wire is electrically connected is the Pd plated layer.

31 . The semiconductor device according to claim 29 ,

wherein a portion of the first lead to which the Al ribbon is electrically connected is the Pd plated layer.

32 . The semiconductor device according to claim 29 ,

wherein the semiconductor chip includes a trench gate power MOSFET, and

wherein the first electrode pad of the semiconductor chip is a source electrode pad.

33 . The semiconductor device according to claim 29 ,

wherein the semiconductor chip includes an insulated gate bipolar transistor, and

wherein the first electrode pad of the semiconductor chip is an emitter electrode pad.

34 . The semiconductor device according to claim 30 ,

wherein the semiconductor chip includes a trench gate power MOSFET, and

wherein the first electrode pad of the semiconductor chip is a source electrode pad and the second electrode pad of the semiconductor chip is a gate electrode pad.

35 . The semiconductor device according to claim 34 ,

wherein an area of the first electrode pad of the semiconductor chip is larger than an area of the second electrode pad of the semiconductor chip.

36 . The semiconductor device according to claim 30 ,

wherein the semiconductor chip includes an insulated gate bipolar transistor, and

wherein the first electrode pad of the semiconductor chip is an emitter electrode pad and the second electrode pad of the semiconductor chip is a gate electrode pad.

37 . The semiconductor device according to claim 36 ,

wherein an area of the first electrode pad of the semiconductor chip is larger than an area of the second electrode pad of the semiconductor chip.