IP Library Granted Patent US 8,775,747
Granted Patent B2
US 8,775,747 · App. 13/847,218 · Granted Jul 8, 2014

Write data mask method and system

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,775,747
App. No.
13/847,218
Granted
Jul 8, 2014
Kind
B2
Abstract

A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.

Claims (46)

1. A method, comprising:

transmitting a data mask comprising a plurality of bits indicating corresponding bytes of multiple bytes of data to be written in a write operation from a first system component to a second system component as a portion of a write command over an address/command line of an interface for coupling the first system component and the second system component, wherein the data is transmitted in a plurality of consecutive bursts during a time period when the write command is a write_mask command.

2. The method of claim 1 , wherein the data mask is transmitted by a first component and stored in a second component to refer to a write to the second component.

3. The method of claim 1 , wherein the data mask is stored in the second component in response to a write_mask command.

4. The method of claim 1 , wherein the write command is a write_with_mask command that directs only indicated bytes to be written.

5. The method of claim 1 , wherein the write command is a write_nomask command that directs all of multiple bytes to be written regardless of the data mask.

6. The method of claim 1 , wherein a write_mask command directs a data mask to be stored for reference during the write operation.

7. The method of claim 1 , further comprising:

determining whether the write operation is a byte-write operation, wherein only particular bytes of the multiple bytes are to be written in response to the write command;

on a condition that the write operation is a byte-write operation, executing a write_mask command; and

storing the data mask in response to the write_mask command.

8. The method of claim 7 , further comprising:

reading the stored data mask; and

writing the particular bytes indicated by the stored data mask.

9. The method of claim 1 , further comprising:

determining whether a write operation is a byte-write operation, wherein only particular bytes of the multiple bytes are to be written in response to the write command; and

on a condition that the write operation is a byte-write operation, transmitting the data mask to be read as a portion of the write command.

10. A system comprising:

a memory component;

an interface that includes a data line and an address/command line;

a processor coupled with the memory component through the interface and configured to:

transmit data to be written in the memory component over the data line;

transmit a write command over the address/command line wherein the write command comprises writing only particular bytes of multiple bytes of the data to be written during a write operation, wherein the data is transmitted in a plurality of consecutive bursts during a time period when the write command is a write_mask command.

11. The system of claim 10 , wherein the data mask is written to the memory component for reference in the write operation in response to the write_mask command.

12. The system of claim 10 , wherein the write command is a write_nomask command, in response to which all of the multiple bytes are written to the memory component regardless of the data mask.

13. The system of claim 10 , wherein the write command is a write_including_mask command that comprises a write command portion and a data mask portion.

14. A non-transitory computer-readable medium having instructions stored thereon, that when executed causes a digital processing system to perform a method, the method comprising:

transmitting a data mask comprising a plurality of bits indicating corresponding bytes of multiple bytes of data to be written in a write operation from a first system component to a second system component as a portion of a write command over an address/command line of an interface coupling the first system component and the second system component, wherein the data is transmitted in a plurality of consecutive bursts during a time period when the write command is a write_mask command.

15. The computer-readable medium of claim 14 , wherein the data mask is transmitted by a first component and stored in a second component to refer to a write to the second component.

16. The computer-readable medium of claim 15 , wherein the data mask is stored in the second component in response to the write_mask command.

17. The computer-readable medium of claim 16 , wherein the write command is a write_with_mask command that directs only indicated bytes to be written.

18. The computer-readable medium of claim 17 , wherein the write command is a write_nomask command that directs all of the multiple bytes to be written regardless of the data mask.

19. The computer-readable medium of claim 17 , wherein the write_mask command directs the data mask to be stored for reference during the write operation.

20. The computer-readable medium of claim 14 , wherein the method further comprises:

determining whether the write operation is a byte-write operation, wherein only particular bytes of the multiple bytes are to be written in response to the write command;

the write operation is a byte-write operation, executing a write_mask command; and

storing the data mask that is transmitted on the address/command line in response to the write_mask command.

21. An integrated circuit comprising:

a memory component;

an interface that includes a data line and an address/command line;

a processor for coupling to an interface having a data line and an/address command line, the processor configured to:

transmit data to be written in a memory component over a data line;

transmit a write command over an address/command line wherein the write command comprises writing only particular bytes of multiple bytes of the data to be written during a write operation, wherein the data is transmitted in a plurality of consecutive bursts during a time period when the write command is a write_mask command.

22. A memory for coupling to an interface which includes a data line and an address/command line, the memory configured to:

receive data to be written in to the memory component over a data line;

receive a write command over an address/command line wherein the write command comprises writing only particular bytes of multiple bytes of the data to be written during a write operation, wherein the data is transmitted in a plurality of consecutive bursts during a time period when the write command is a write_mask command.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2024
From: ATI TECHNOLOGIES ULC
To: ONESTA IP, LLC
Reel/Frame 069379/0556 →
CHANGE OF NAME Recorded Jul 12, 2021
From: ATI TECHNOLOGIES INC.
To: ATI TECHNOLOGIES ULC
Reel/Frame 056890/0257 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2021
From: MACRI, JOSEPH D.; MOREIN, STEPHEN; LEE, MING-JU E.; CHEN, LIN
To: ATI TECHNOLOGIES, INC.
Reel/Frame 056802/0350 →