Multi-core online patching method and apparatus

1. A multi-core online patching method comprising:

receiving a patch at a processor, wherein the processor comprises multiple cores and wherein the processor is coupled to a memory;

separating shared global variables and private global variables defined in the patch;

mapping the shared global variables to a shared data segment in a patch area by using a mapping mode of a memory address, wherein the shared global variables are obtained directly from the memory using the memory address; and

mapping the private global variables to private data segments in the patch area by using a mapping mode of a cache bus access address,

wherein the patch area comprises a shared area, a private area, and a backup area,

wherein the shared area comprises the shared data segment,

wherein the private area comprises the private data segments,

wherein the backup area comprises the private data segments, wherein the private data segments in the backup area restore the private data segments to one of the multiple cores after the one of the multiple cores is reset,

wherein the private data segments comprise multiple different segments,

wherein each one of the multiple different segments of the private data segments corresponds to one of the multiple cores of the processor,

wherein each one of the private global variables corresponds to one of the multiple cores of the processor, and

wherein the private global variables are mapped to the private data segments according to the multiple cores of the processor.

2. The method according to claim 1 , wherein separating the shared global variables and the private global variables defined in the patch comprises:

defining the private global variables in the patch as structure variables, wherein a size of a structure is a size of a private data segment of each core that is in the patch area;

segmenting remaining space by using a segmentation number after defining member variables of the structure variables is completed, where data before the segmentation number is valid data; and

placing the shared global variables and the private global variables in the patch into different data segments when a patch file is written.

3. The method according to claim 2 , wherein mapping the private global variables to the private data segments in the patch area by using the mapping mode of the variable address specified by the user comprises:

extracting valid data of the private global variables; and

mapping, according to the size of the defined structure, the valid data to the private data segment of each core that is in the patch area by using a mapping mode of the memory address or by using a mapping mode of the cache bus access address mapping.

4. The method according to claim 1 , further comprising backing up a function instruction of a core private memory and core private data to the data backup area in the patch area.

5. The method according to claim 4 , further comprising:

configuring a synchronous mask table with a same image for all cores when the patch is initialized;

removing a synchronous mask flag of an abnormal core from the synchronous mask table when a certain core in the multiple cores is abnormal and when the abnormal core is in the synchronous mask table;

restoring the abnormal core to a patch status according to the data backup area in the patch area after the abnormal core is reset;

re-adding the removed synchronous mask flag to the synchronous mask table after the patch status is restored on the abnormal core successfully; and

sending, by an operation core, a synchronization event to an online slave core according to the latest synchronous mask table when the patch is activated.

6. The method according to claim 1 , wherein the multiple cores comprise a first core, a second core, and a third core, wherein the private data segments comprise a first core private data segment, a second core private data segment, and a third core private data segment, wherein a portion of the private global variables that corresponds to the first core is stored to the first core private data segment, wherein a portion of the private global variables that corresponds to the second core is stored to the second core private data segment, and wherein a portion of the private global variables that corresponds to the third core is stored to the third core private data segment.

7. A multi-core online patching apparatus comprising:

a memory; and

a processor coupled to the memory and configured to:

receive a patch, wherein the processor comprises multiple cores;

separate shared global variables and private global variables defined in the patch; and

map the shared global variables to a shared data segment in a patch area by using a mapping mode of a memory address, wherein the shared global variables are obtained directly from the memory using the memory address, and

map the private global variables to private data segments in the patch area by using a mapping mode of a cache bus access address,

wherein the patch area comprises a shared area, a private area, and a backup area,

wherein the shared area comprises the shared data segment,

wherein the private area comprises the private data segments,

wherein, the backup area comprises the private data segments, wherein the private data segments in the backup area restore the private data segments to one of the multiple cores after the one of the multiple cores is reset,

wherein the private data segments comprise multiple different segments,

wherein each one of the multiple different segments of the private data segments corresponds to one of the multiple cores of the processor,

wherein each one of the private global variables corresponds to one of the multiple cores of the processor, and

wherein the private global variables are mapped to the private data segments according to the multiple cores of the processor.

8. The apparatus according to claim 7 , wherein the processor is further configured to:

define the private global variables in the patch as structure variables, wherein a size of a structure is a size of a private data segment of each core that is in the patch area;

after completing defining member variables of the structure variables, segment the remaining space by using a segmentation number, wherein data before the segmentation number is valid data; and

when a patch file is written, place the shared global variables and the private global variables in the patch in different data segments.

9. The apparatus according to claim 7 , wherein the processor is further configured to back up a function instruction of a core private memory and core private data to the data backup area in the patch area.

10. The apparatus according to claim 9 , wherein the processor is further configured to:

configure a synchronous mask table with a same image for all cores when the patch is initialized;

remove a synchronous mask flag of an abnormal core from the synchronous mask table when a certain core in the multiple cores is abnormal and when the abnormal core is in the synchronous mask table;

restore the abnormal core to a patch status according to the data backup area in the patch area after the abnormal core is reset; and

re-add the removed synchronous mask flag to the synchronous mask table after the patch status is restored on the abnormal core successfully.

11. The apparatus according to claim 10 , wherein the processor is further configured to, when the patch is activated, initiate, by an operation core, a synchronization event to an online slave core according to the latest synchronous mask table processed by the mask table processing unit.

12. The apparatus according to claim 7 , wherein the multiple cores comprise a first core, a second core, and a third core, wherein the private data segments comprise a first core private data segment, a second core private data segment, and a third core private data segment, wherein a portion of the private global variables that corresponds to the first core is stored to the first core private data segment, wherein a portion of the private global variables that corresponds to the second core is stored to the second core private data segment, and wherein a portion of the private global variables that corresponds to the third core is stored to the third core private data segment.

13. A non-transitory computer-readable medium having computer executable instructions for performing a method comprising:

receiving a patch at a processor, wherein the processor comprises multiple cores, and wherein the processor is coupled to a memory;

separating shared global variables and private global variables defined in the patch;

mapping the shared global variables to a shared data segment in a patch area by using a mapping mode of a memory address, wherein the shared global variables are obtained directly from the memory using the memory address; and

mapping the private global variables to private data segments in the patch area by using a mapping mode of a cache bus access address,

wherein the patch area comprises a shared area, a private a, and a backup area,

wherein the shared area comprises the shared data segment,

wherein the private area comprises the private data segments,

wherein the backup area comprises the private data segments, wherein the private data segments in the backup area restore the private data segments to one of the multiple cores after the one of the multiple cores is reset,

wherein the private data segments comprise multiple different segments,

wherein each one of the multiple different segments of the private data segments corresponds to one of the multiple cores of the processor,

wherein each one of the private global variables corresponds to one of the multiple cores of the processor, and

wherein the private global variables are mapped to the private data segments according to the multiple cores of the processor.

14. The method according to claim 6 , wherein the patch area comprises a shared code segment, a shared data segment, the first core private data segment, the second core private data segment, the third core private data segment, and the backup area.

15. The apparatus according to claim 12 , wherein the patch area comprises a shared code segment, a shared data segment, the first core private data segment, the second core private data segment, the third core private data segment, and the backup area.

16. The non-transitory computer-readable medium according to claim 13 , wherein the multiple cores comprise a first core, a second core, and a third core, wherein the private data segments comprise a first core private data segment, a second core private data segment, and a third core private data segment, wherein a portion of the private global variables that corresponds to the first core is stored to the first core private data segment, wherein a portion of the private global variables that corresponds to the second core is stored to the second core private data segment, and wherein a portion of the private global variables that corresponds to the third core is stored to the third core private data segment.

17. The non-transitory computer-readable medium according to claim 16 , wherein the patch area comprises a shared code segment, a shared data segment, the first core private data segment, the second core private data segment, the third core private data segment, and the backup area.

18. The non-transitory computer-readable medium according to claim 13 , wherein the multiple cores comprise a first core, a second core, and a third core, wherein the private data segments comprise a first core private data segment, a second core private data segment, and a third core private data segment, wherein a portion of the private global variables that corresponds to the first core is stored to the first core private data segment, wherein a portion of the private global variables that corresponds to the second core is stored to the second core private data segment, and wherein a portion of the private global variables that corresponds to the third core is stored to the third core private data segment.

19. The non-transitory computer-readable medium according to claim 18 , wherein the patch area comprises a shared code segment, a shared data segment, the first core private data segment, the second core private data segment, the third core private data segment, and the backup area.

20. The non-transitory computer-readable medium according to claim 13 , wherein the computer executable instructions for performing the method further comprise backing up a function instruction of a core private memory and core private data to the data backup area in the patch area.