Nonvolatile semiconductor memory device

1. A nonvolatile semiconductor memory device including a memory cell region provided with a plurality of memory cells, and a peripheral region provided around the memory cell region, the device comprising:

a foundation layer provided in the memory cell region and in the peripheral region, the foundation layer including a plurality of wiring layers and a plurality of device elements; and

a stacked body provided on the foundation layer, the stacked body including a plurality of electrode layers and a plurality of intermediate layers alternately stacked,

the memory cell region including:

a first channel body layer penetrating through the stacked body and the first channel body layer extending from an upper surface of the stacked body to a lower surface of the stacked body;

a memory film provided between first channel body layer and each of the plurality of electrode layers;

a pair of select gate electrodes provided on the stacked body;

a second channel body layer penetrating through each of the pair of select gate electrodes and the second channel body layer being connected to the first channel body layer; and

a gate insulating film provided between each of the pair of select gate electrodes and the second channel body layer, and the peripheral region including:

an interlayer insulating film provided on the stacked body; and

an electrode pad provided on the interlayer insulating film, a bonding wire being capable of being bonded to the electrode pad, at least one of the plurality of wiring layers being provided below the electrode pad.

2. The device according to claim 1 , wherein the cell region further includes a bit line connected to the second channel body layer connected to the first channel body layer, and a position of the electrode pad is higher than a position of the bit line.

3. The device according to claim 1 , wherein a portion of the stacked body below the electrode pad is electrically insulated from the stacked body other than the portion.

4. The device according to claim 1 , wherein

the peripheral region further includes a first via connected to the electrode pad between the electrode pad and the stacked body, and

the first via is located below the electrode pad and further surrounded with the interlayer insulating film.

5. The device according to claim 4 , wherein

the peripheral region further includes a first conductive layer connected to the first via between the electrode pad and the stacked body, and

the first conductive layer is located below the first via and further surrounded with the interlayer insulating film.

6. The device according to claim 5 , wherein

the peripheral region further includes a second via connected to the first conductive layer between the electrode pad and the stacked body, and

the second via is located below the first conductive layer and further surrounded with the interlayer insulating film.

7. The device according to claim 6 , wherein

the peripheral region further includes a second conductive layer connected to the second via between the electrode pad and the stacked body, and

the second conductive layer is located below the second via and further surrounded with the interlayer insulating film.

8. The device according to claim 7 , wherein the peripheral region further includes a third via connected to the second conductive layer below the second conductive layer.

9. The device according to claim 8 , wherein

a portion of the stacked body below the electrode pad is electrically insulated from the stacked body other than the portion,

the third via is provided between the foundation layer and the second conductive layer, and

the third via is further electrically insulated from the portion of the stacked body.

10. The device according to claim 8 , wherein the third via is electrically connected to one of the plurality of wiring layers.

11. The device according to claim 10 , wherein the one of the plurality of wiring layers connected to the third via is located below the electrode pad.

12. The device according to claim 3 , wherein the electrode pad bypasses the portion of the stacked body below the electrode pad and is electrically connected to one of the plurality of wiring layers.

13. The device according to claim 7 , wherein

the peripheral region further includes an insulating layer in contact with the second conductive layer below the second conductive layer, and

the insulating layer penetrates through the stacked body.

14. The device according to claim 13 , wherein the insulating layer includes a low-k material.

15. The device according to claim 5 , wherein

the cell region further includes a bit line connected to the second channel body layer connected to the first channel body layer, and

height from the foundation layer and material of the bit line are same as height from the foundation layer and material of the first conductive layer.

16. The device according to claim 7 , wherein

the cell region further includes a source line connected to the second channel body layer connected to the first channel body layer, and

height from the foundation layer and material of the source line are same as height from the foundation layer and material of the second conductive layer.

17. The device according to claim 1 , wherein

the cell region further includes a different wiring layer on the bit line, and

height from the foundation layer and material of the different wiring layer are same as height from the foundation layer and material of the electrode pad.

18. The device according to claim 1 , wherein at least one of the plurality of device elements is placed below the electrode pad.

19. The device according to claim 1 , wherein at least one of the plurality of device elements and at least one of the plurality of wiring layers are placed below the electrode pad.

20. The device according to claim 1 , wherein the plurality of intermediate layers include silicon or silicon oxide.