IP Library Granted Patent US 8,996,962
Granted Patent B2
US 8,996,962 · App. 13/848,624 · Granted Mar 31, 2015

Chase coding for error correction of encrypted packets with parity

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Quick Facts
Patent No.
US 8,996,962
App. No.
13/848,624
Granted
Mar 31, 2015
Kind
B2
Abstract

A plurality of encrypted packets having common payload data are received, wherein each of the plurality of encrypted packets includes a corresponding parity check field, and wherein a corresponding parity check syndrome for each of the plurality of encrypted packets indicates at least one bit error. A payload portion of each of the plurality of encrypted packets is decrypted to generate a plurality of decrypted payload portions. At least one chase coding technique is used to generate a corrected decrypted payload, based on at least one candidate bit error position and further based on the corresponding parity check syndrome for at least one of the plurality of encrypted packets.

Claims (44)

1. An apparatus, comprising:

a receiver for receiving a plurality of encrypted packets having common payload data, wherein each of the plurality of encrypted packets includes a corresponding parity check field, wherein a corresponding parity check syndrome for each of the plurality of encrypted packets indicates at least one bit error;

a processing circuit coupled to the receiver to:

decrypt a payload portion of each of the plurality of encrypted packets to generate a plurality of decrypted payload portions; and

apply at least one chase coding technique to generate a corrected decrypted payload, based on a plurality of candidate bit error positions and further based on the corresponding parity check syndrome for at least one of the plurality of encrypted packets.

2. The apparatus of claim 1 wherein the processing circuit is further operable to:

compare the plurality of decrypted payload portions to generate the plurality of candidate bit error positions in the plurality of decrypted payload portions.

3. The apparatus of claim 1 wherein the plurality of candidate bit error positions is generated based on symbol reliability data.

4. The apparatus of claim 1 wherein the at least one chase coding technique includes:

calculating a parity check syndrome corresponding to each of the plurality of candidate bit error positions;

comparing the parity check syndrome corresponding to the plurality of candidate bit error positions to selected ones of the corresponding parity check syndrome for each of the plurality of encrypted packets; and

selectively correcting a selected one of the plurality of decrypted payload portions when the parity check syndrome for one of the plurality of encrypted packets matches the parity check syndrome corresponding to one of the plurality of candidate bit error positions.

5. The apparatus of claim 4 wherein the processing circuit is further operable to:

indicate an uncorrectable error condition when none the parity check syndromes for the plurality of encrypted packets matches the parity check syndrome corresponding to any of the plurality of candidate bit error positions.

6. The apparatus of claim 1 wherein the plurality of encrypted packets include an original transmission and at least one retransmission and the at least one chase coding technique includes a plurality of chase coding techniques.

7. The apparatus of claim 6 wherein the plurality of chase coding techniques includes a chase coding technique that generates the at least one candidate bit error position based on a comparison of two of the plurality of decrypted payload portions.

8. The apparatus of claim 6 wherein the plurality of chase coding techniques includes a chase coding technique that generates the at least one candidate bit error position based on a comparison of at least three of the plurality of decrypted payload portions.

9. An apparatus, comprising:

a receiver for receiving a plurality of encrypted packets having common payload data, wherein each of the plurality of encrypted packets includes a corresponding parity check field, wherein a corresponding parity check syndrome for each of the plurality of encrypted packets indicates at least one bit error;

a processing circuit coupled to the receiver to:

decrypt a payload portion of each of the plurality of encrypted packets to generate a plurality of decrypted payload portions; and

apply at least one chase coding technique to generate a corrected decrypted payload, based on at least one candidate bit error position and further based on the corresponding parity check syndrome for at least one of the plurality of encrypted packets.

10. The apparatus of claim 9 wherein the processing circuit is further operable to:

compare the plurality of decrypted payload portions to generate the at least one candidate bit error position in the plurality of decrypted payload portions.

11. The apparatus of claim 9 wherein the at least one candidate bit error position is generated based on symbol reliability data.

12. The apparatus of claim 9 wherein the at least one chase coding technique includes:

calculating a parity check syndrome corresponding to each of the at least one candidate bit error position;

comparing the parity check syndrome corresponding to the at least one candidate bit error position to selected ones of the corresponding parity check syndrome for each of the plurality of encrypted packets; and

selectively correcting a selected one of the plurality of decrypted payload portions the parity check syndrome for one of the plurality of encrypted packets matches the parity check syndrome corresponding to the at least one candidate bit error position.

13. The apparatus of claim 12 wherein the processing circuit is further operable to:

indicate an uncorrectable error condition when none the parity check syndromes for the plurality of encrypted packets matches the parity check syndrome corresponding to the at least one candidate bit error position.

14. The apparatus of claim 9 wherein the plurality of encrypted packets include an original transmission and at least one retransmission and the at least one chase coding technique includes a plurality of chase coding techniques.

15. The apparatus of claim 14 wherein the plurality of chase coding techniques includes a chase coding technique that generates the at least one candidate bit error position based on a comparison of two of the plurality of decrypted payload portions.

16. The apparatus of claim 14 wherein the plurality of chase coding techniques includes a chase coding technique that generates the at least one candidate bit error position based on a comparison of at least three of the plurality of decrypted payload portions.

17. A method, comprising:

receiving a plurality of encrypted packets having common payload data, wherein each of the plurality of encrypted packets includes a corresponding parity check field, wherein a corresponding parity check syndrome for each of the plurality of encrypted packets indicates at least one bit error;

decrypting a payload portion of each of the plurality of encrypted packets to generate a plurality of decrypted payload portions; and

applying at least one chase coding technique to generate a corrected decrypted payload, based on at least one candidate bit error position in the plurality of decrypted payload portions and further based on the corresponding parity check syndrome for at least one of the plurality of encrypted packets.

18. The method of claim 17 wherein the at least one chase coding technique includes:

calculating a parity check syndrome corresponding to each of the at least one candidate bit error position;

comparing the parity check syndrome corresponding to the at least one candidate bit error position to selected ones of the corresponding parity check syndrome for each of the plurality of encrypted packets; and

selectively correcting a selected one of the plurality of decrypted payload portions the parity check syndromes for one of the plurality of encrypted packets matches the parity check syndrome corresponding to the at least one candidate bit error position.

19. The method of claim 17 wherein the at least one chase coding technique includes a chase coding technique that generates the at least one candidate bit error position based on a comparison of two of the plurality of decrypted payload portions.

20. The method of claim 17 wherein the at least one chase coding technique includes a chase coding technique that generates the at least one candidate bit error position based on a comparison of at least three of the plurality of decrypted payload portions.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2013
From: ZOPF, ROBERT W.; DESAI, PRASANNA; GRUNERT, NORBERT
To: BROADCOM CORPORATION
Reel/Frame 030063/0608 →