IP Library Granted Patent US 9,698,273
Granted Patent B2
US 9,698,273 · App. 13/849,978 · Granted Jul 4, 2017

Thin film transistor, method of manufacturing the same, display unit, and electronic apparatus

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Quick Facts
Patent No.
US 9,698,273
App. No.
13/849,978
Granted
Jul 4, 2017
Kind
B2
Abstract

A thin film transistor includes: a gate electrode and a pair of source-drain electrodes provided on a substrate; an oxide semiconductor layer provided between the gate electrode and the pair of source-drain electrodes, the oxide semiconductor layer forming a channel; a protection film provided over whole of a surface above the substrate; and a gate insulating film provided on a gate electrode side of the oxide semiconductor layer, the gate insulating film having end faces part or all of which are covered with the pair of source-drain electrodes or with the protection film.

Claims (27)

1. A thin film transistor comprising:

a gate electrode and a pair of source-drain electrodes provided on a substrate;

an oxide semiconductor layer provided between the gate electrode and the pair of source-drain electrodes, the oxide semiconductor layer forming a channel;

a channel protective film formed on the channel of the oxide semiconductor layer;

a protection film provided over whole of a surface above the substrate, a portion of the channel protective film being formed between the protection film and the oxide semiconductor layer in a thickness direction of the thin film transistor; and

a gate insulating film provided on a gate electrode side of the oxide semiconductor layer, and configured of one of a single film and a lamination film, the lamination film including a plurality of films,

wherein the pair of source-drain electrodes cover the entire end faces of the single film of the gate insulating film or cover the entire end faces of each of the films in the lamination film of the gate insulating film, and cover at least part of each of a plurality of side faces of the gate insulating film.

2. The thin film transistor according to claim 1 , wherein the gate electrode, the gate insulating film, the oxide semiconductor layer, the pair of source-drain electrodes, and the protective film are provided on the substrate in recited order.

3. The thin film transistor according to claim 2 , wherein the pair of source-drain electrodes cover a surface exposed from the oxide semiconductor layer of the gate insulating film.

4. The thin film transistor according to claim 1 , wherein the channel protective film has a width in plan view that is less than a corresponding width of the source and drain electrodes in plan view such that source and drain electrodes cover at least portions of at least three edge surfaces of the channel protective film.

5. The thin film transistor according to claim 1 , wherein in plan view the gate electrode has a first width in an area not covered by the source and drain electrodes that is less than a second width in an area that is covered by the source and drain electrodes.

6. The thin film transistor according to claim 1 , wherein the gate insulating film is patterned in an island-like shape.

7. A display unit with a plurality of display devices and a plurality of thin film transistors driving the display devices, the plurality of thin film transistors each comprising:

a gate electrode and a pair of source-drain electrodes provided on a substrate;

an oxide semiconductor layer provided between the gate electrode and the pair of source-drain electrodes, the oxide semiconductor layer forming a channel;

a channel protective film formed on the channel of the oxide semiconductor layer;

a protection film provided over whole of a surface above the substrate, a portion of the channel protective film being formed between the protection film and the oxide semiconductor layer in a thickness direction of the thin film transistor; and

a gate insulating film provided on a gate electrode side of the oxide semiconductor layer, and configured of one of a single film and lamination film, the lamination film including a plurality of films,

wherein the pair of source-drain electrodes cover the entire end faces of the single film of the gate insulating film or cover the entire end faces of each of the films in the lamination film of the gate insulating film, and cover at least part of each of a plurality of side faces of the gate insulating film.

8. The display unit according to claim 7 , wherein the gate insulating film is separated between adjacent thin film transistors of the plurality of thin film transistors.

9. An electronic apparatus with a display unit with a plurality of display devices and a plurality of thin film transistors driving the display devices, the plurality of thin film transistors each comprising:

a gate electrode and a pair of source-drain electrodes provided on a substrate;

an oxide semiconductor layer provided between the gate electrode and the pair of source-drain electrodes, the oxide semiconductor layer forming a channel;

a channel protective film formed on the channel of the oxide semiconductor layer;

a protection film provided over whole of a surface above the substrate, and a portion of the channel protective film is formed between the protection film and the oxide semiconductor layer in a thickness direction of the thin film transistor; and

a gate insulating film provided on a gate electrode side of the oxide semiconductor layer, and configured of one of a single film and a lamination film, the lamination film including a plurality of films,

wherein the pair of source-drain electrodes cover the entire end faces of the single film of the gate insulating film or cover the entire end faces of each of the films in the lamination film of the gate insulating film, and cover at least part of each of a plurality of side faces of the gate insulating film.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY DATA PREVIOUSLY RECORDED AT REEL: 035616 FRAME: 0124. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 26, 2015
From: SONY CORPORATION
To: JOLED INC.
Reel/Frame 035771/0551 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2015
From: SONY CORPORATION
To: JOLED INC
Reel/Frame 035616/0124 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 5, 2013
From: KINOSHITA, TOMOATSU
To: SONY CORPORATION
Reel/Frame 030159/0098 →