Upgrading a programmable logic gate array in an in-service pluggable transceiver

1. A programmable pluggable transceiver for use in a network element of a network, the transceiver comprising:

a datapath for relaying frames through the transceiver;

a memory for storing upgrade data;

a programmable logic gate array connected through the datapath, connected to the memory, and comprising internal logic, core logic, connectivity logic and control logic;

the internal logic partitioned from the core logic, connectivity logic and control logic in the programmable logic gate array for upgrading the internal logic while the core logic, control logic and connectivity logic remain operational;

the internal logic, core logic, and control logic each connected to the datapath for receiving and processing different frames;

the internal logic connected to the connectivity logic via the control logic for, except during a partial upgrade, sending frames on the datapath and sending selection signals to the connectivity logic;

the core logic connected to the connectivity logic for forwarding frames through the datapath in accordance with a minimum throughput requirement;

the connectivity logic connected to the core logic and the control logic for receiving frames on the datapath and sending those frames on the datapath in accordance with the selection signal received from the control logic;

the control logic connected to the internal logic for receiving frames and selection signals from the internal logic;

the control logic connected to the connectivity logic for sending frames and selection signals received from the internal logic, except during a partial upgrade;

the control logic, in response to receiving a frame on the datapath containing upgrade data, sending the upgrade data to the memory;

the control logic, in response to receiving a frame on the datapaths containing a partial upgrade command:

blocking the internal logic from sending frames or selection signals to the connectivity logic before and during the partial upgrade,

triggering upgrade of the internal logic from upgrade data in the memory while the core logic, connectivity logic and control logic remain operational during the partial upgrade, and

unblocking the internal logic from sending frames or selection signals to the connectivity logic after the partial upgrade.

2. The programmable pluggable transceiver of claim 1 wherein the core logic and the connectivity logic relay frames through the transceiver on the datapath while the control logic responds to the partial upgrade command.

3. The programmable pluggable transceiver of claim 1 wherein the control logic comprises logic gates and mask signals for blocking the frames and selection signals from the internal logic thereby blocking the internal logic's frames and selection signals from reaching the connectivity logic.

4. The programmable pluggable transceiver of claim 1 wherein the control logic further comprises upgrade frame processing logic and upgrade logic;

the upgrade frame processing logic for receiving frames on the datapath including frames containing upgrade data to be stored in the memory and frames containing partial upgrade commands to be forwarded to the upgrade logic;

the upgrade logic for isolating and triggering upgrade of the internal logic.

5. The programmable pluggable transceiver of claim 4 wherein the upgrade logic comprises further logic for determining if the internal logic is inserting frames on the datapath when the control logic receives a partial upgrade command, and if so, concluding the frame inserting before blocking the internal logic from sending frames or selection signals

wherein concluding the frame inserting comprises any of:

waiting for an idle period after the currently inserting frames;

waiting for the currently inserting frames to complete insertion; and

aborting the currently inserting frames by invalidating a checksum of the current frame and stopping further frame insertion.

6. The programmable pluggable transceiver of claim 5 wherein the upgrade logic unblocking the internal logic from sending frames or selection signals to the connectivity logic after the partial upgrade further comprises logic for re-enabling frame inserting in the internal logic.

7. The programmable pluggable transceiver of claim 1 further comprising:

a second datapath for relaying frames through the transceiver in a different direction than the datapath;

the internal logic including loopback logic for filtering frames from one of the datapath and the second datapath and sending the frames back on the other of the datapath and the second datapath.

8. The programmable pluggable transceiver of claim 1 wherein the control logic comprises further logic for authenticating the partial upgrade command before upgrading the internal logic.

9. The programmable pluggable transceiver of claim 1 wherein the control logic comprises further logic for verifying an encryption of the frame containing upgrade data before sending the upgrade data to the memory.

10. The programmable pluggable transceiver of claim 1 wherein the control logic blocking the internal logic from sending frames or selection signals to the connectivity logic before and during the partial upgrade comprises further logic for switching the connectivity logic to a pass-through mode; and

unblocking the internal logic from sending frames or selection signals to the connectivity logic after the partial upgrade comprises further logic for releasing the connectivity logic from the pass-through mode.

11. A method for partially upgrading a programmable pluggable transceiver in service in a network, the transceiver having a datapath for relaying frames through the transceiver, a programmable logic gate array connected through the datapath and a memory connected to the programmable logic gate array, the programmable logic gate array including upgradeable internal logic, core logic, connectivity logic and control logic, the internal logic, core logic and control logic connected to the datapath for receiving and processing different frames, the core logic and control logic each connected to the connectivity logic for sending frames to be sent on the datapath, the connectivity logic receiving frames from the core logic and the control logic on the datapath and sending those frame on the datapath in accordance with a selection signal from the control logic, the core logic for forwarding frames on the datapath in accordance with a minimum throughput requirement, the internal logic connected to the control logic for forwarding frames and selection signals to the connectivity logic, except during a partial upgrade, the control logic for isolating and triggering upgrade of the internal logic while the core logic, connectivity logic and control logic remain operational during the partial upgrade, the method comprising:

partitioning the internal logic separately from the core logic, connectivity logic and control logic for upgrading the internal logic while the core logic, control logic and connectivity logic remain operational;

providing upgrade data in the memory;

receiving, in the control logic, a frame containing a partial upgrade command, and in response, the control logic:

blocking the internal logic from sending frames or selection signals to the connectivity logic;

after the blocking, triggering reprogramming of the internal logic from the upgrade data in the memory while the core logic, connectivity logic and control logic remain operational; and

after the reprogramming, unblocking the internal logic from sending frames or selection signals to the connectivity logic.

12. The method of claim 11 further comprising relaying frames through the transceiver via the core logic and the connectivity logic, on the datapath during the blocking, the reprogramming and the unblocking.

13. The method of claim 11 wherein blocking the internal logic from sending frames or selection signals to the connectivity logic further comprises:

masking, in the control logic, the frames and selection signals from the internal logic thereby blocking the internal logic's frames and selection signals from reaching the connectivity logic.

14. The method of claim 11 further comprising:

receiving, in the control logic, a frame containing upgrade data and in response, storing the upgrade data in the memory; and

receiving, in the control logic, a frame containing a partial upgrade command and in response, isolating the internal logic then triggering upgrade of the internal logic.

15. The method of claim 11 further comprising: in response to receiving, in the control logic, a frame containing a partial upgrade command, determining if the internal logic is inserting frames on the datapath, and if so, concluding inserting frames before the blocking;

wherein concluding inserting frames comprises any of:

waiting for an idle period after the currently inserting frames;

waiting for the currently inserting frames to complete insertion; and

aborting the currently inserting frames by invalidating a checksum of the current frame and stopping further frame insertion.

16. The method of claim 15 wherein the unblocking further comprises re-enabling frame inserting in the internal logic.

17. The method of claim 11 further comprising:

providing a second datapath for relaying frames through the transceiver in a different direction than the datapath;

filtering, in the internal logic, frames from one of the datapath and the second datapath and sending the filtered frames back on the other of the datapath and the second datapath.

18. The method of claim 11 further comprising in response to receiving, in the control logic, a frame containing a partial upgrade command, authenticating the partial upgrade command before the blocking.

19. The method of claim 11 further comprising in response to receiving, in the control logic, a frame containing upgrade data, verifying an encryption of the frame containing upgrade data.

20. The method of claim 11 wherein the blocking further comprises switching the connectivity logic to a pass-through mode; and the unblocking further comprises releasing the connectivity logic from the pass-through mode.