System and method for data flow identification and alignment in a 40/100 gigabit ethernet gearbox

1. A device, comprising:

a plurality of inputs for receiving a corresponding first plurality of channels carrying a plurality of data flows, each of the first plurality of channels carried on a physical lane of a first set of physical lanes;

a data flow identifier module configured to identify data flow identifiers contained within the plurality of data flows; and

a bit de-multiplexer configured to de-multiplex bits from the first plurality of channels into a second plurality of channels that have a lower bit rate as compared to the first plurality of channels, wherein an ordering of bits that are de-multiplexed into the second plurality of channels is based on an identity of the data flow identifiers identified by the data flow identifier module, the bit de-multiplexer also configured to output each of the second plurality of channels onto an assigned physical lane of a second set of physical lanes corresponding to a physical lane of a set of input physical lanes of a multiplexer in accordance with a stored channel assignment definition that maps data flow identifiers to physical lanes, the stored channel assignment definition ensuring that a channel having a particular data flow identifier is always output on the same physical lane that is pre-assigned to the particular data flow identifier based on the input physical lanes of the multiplexers;

wherein the data flow identifier information is fed back from the data flow identifier module to the bit de-multiplexer.

2. The device of claim 1 , wherein the second plurality of channels are 10 Gbit/s channels.

3. The device of claim 2 , wherein the first plurality of channels are 25 Gbit/s channels.

4. The device of claim 1 , wherein the bit de-multiplexer receives data flow identifier information from the virtual lane identifier module.

5. The device of claim 4 , wherein the data flow identifier information is fed forward from the data flow identifier module to the bit de-multiplexer.

6. The device of claim 1 , wherein the data flow identifiers are defined by IEEE 802.3ba.

7. A method, comprising:

receiving, at a plurality of inputs in a device, a first channel and a second channel of a plurality of channels carrying a plurality of data flows;

identifying, by a data flow identifier module in the device, data flow identifiers contained within the plurality of data flows;

feeding back data flow identifier information from the data flow identifier module to a bit de-multiplexer of the device;

generating, by the bit de-multiplexer, a first channel and a second channel of a second plurality of channels from the first plurality of channels, wherein an ordering of bits that are de-multiplexed into the second plurality of channels is based on the data flow identifier information fed back by the data flow identifier module, and

outputting the first channel of the second plurality of channels onto an assigned first physical lane and the second channel of the second plurality of channels onto an assigned second physical lane, in accordance with a stored channel assignment definition that maps data flow identifiers to physical lanes, the stored channel assignment definition ensuring that a channel having a particular data flow identifier is always output on the same physical lane that is pre-assigned to the particular data flow identifier based on input physical lanes of a multiplexer.

8. The method of claim 7 , wherein the second plurality of channels are 10 Gbit/s channels.

9. The method of claim 7 , wherein the second plurality of channels are 25 Gbit/s channels.

10. The method of claim 7 , further comprising feeding forward data flow identifier information from the data flow identifier module to the bit de-multiplexer.

11. The method of claim 7 , wherein the data flow identifiers are defined by IEEE 802.3ba.

12. A method, comprising:

receiving, at a plurality of inputs in a device, a plurality of 25 Gbit/s channels carrying a plurality of data flows;

identifying, by a data flow identifier module in the device, data flow identifiers contained within the plurality of data flows;

feeding back data flow identifier information from the data flow identifier module to a bit de-multiplexer;

generating, by the bit de-multiplexer having a 2:5 ratio in the device, a plurality of 10 Gbit/s channels from the plurality of 25 Gbit/s channels, wherein an ordering of bits that are de-multiplexed into the plurality of 10 Gbit/s channels is based on the data flow identifier information fed back by the data flow identifier module;

aligning each of the plurality of 10 Gbit/s channels onto an assigned physical lane in accordance with a stored channel assignment definition that maps data flow identifiers to physical lanes, the stored channel assignment definition ensuring that a channel having a particular data flow identifier is always output on the same physical lane that is pre-assigned to the particular data flow identifier based on a corresponding input physical lane at a bit multiplexer outputting the plurality of 25 Gbit/s channels; and

outputting each of the plurality of 10 Gbit/s channels onto the assigned physical lane.

13. The method of claim 12 , further comprising feeding forward data flow identifier information from the data flow identifier module to the bit de-multiplexer.

14. The method of claim 12 , wherein the data flow identifiers are defined by IEEE 802.3ba.