Method of manufacturing semiconductor device, solid-state imaging device, and solid-state imaging apparatus
View Patent ↗A method of manufacturing a semiconductor device includes the steps of forming a gate electrode of a transistor on an insulator layer on a surface of a semiconductor substrate, forming an isolation region by performing ion implantation of an impurity of a first conductivity type into the semiconductor substrate, forming a lightly doped drain region by performing, after forming a mask pattern including an opening portion narrower than a width of the gate electrode on an upper layer of the gate electrode of the transistor, ion implantation of an impurity of a second conductivity type near the surface of the semiconductor substrate with the mask pattern as a mask, and forming a source region and a drain region of the transistor by performing ion implantation of an impurity of the second conductivity type into the semiconductor substrate after forming the gate electrode of the transistor.
1. A solid-state imaging device comprising:
a photoelectric conversion unit configured to store a signal charge according to incident light; and
a semiconductor device including an isolation region which is an impurity region of a first conductivity type, a source region and a drain region of a transistor which are impurity regions of a second conductivity type, a gate electrode of the transistor which is provided on an insulator layer on a surface of a semiconductor substrate formed with the isolation region and the source region and the drain region of the transistor, and a lightly doped drain region of the second conductivity type which is provided near the surface of the semiconductor substrate in a region narrower than a width of the gate electrode of the transistor.
2. A solid-state imaging apparatus comprising:
a photoelectric conversion unit configured to store a signal charge according to incident light;
a semiconductor device including an isolation region which is an impurity region of a first conductivity type, a source region and a drain region of a transistor which are impurity regions of a second conductivity type, a gate electrode of the transistor which is provided on an insulator layer on a surface of a semiconductor substrate formed with the isolation region and the source region and the drain region of the transistor, and a lightly doped drain region of the second conductivity type which is provided near the surface of the semiconductor substrate in a region narrower than a width of the gate electrode of the transistor; and
an optical system configured to direct the incident light to the photoelectric conversion unit.
3. The solid-state imaging apparatus according to claim 2 , wherein a width of the lightly doped drain region is approximately equivalent to a width of the source region and the drain region of the transistor or narrower than the width of the source region and the drain region of the transistor.
4. The solid-gate imaging apparatus according to claim 2 , wherein the lightly doped drain region does not exist outside of the gate electrode of the transistor in the width direction.
5. The solid-state imaging apparatus according to claim 4 , wherein the width of the gate electrode refers to the length of the gate electrode in the width direction of the current path of the transistor.
6. The solid-state imaging apparatus according to claim 2 , wherein the lightly doped drain region is narrower near the surface of the semiconductor substrate than a distance from the semiconductor surface.
7. The solid-state imaging device according to claim 1 , wherein a width of the lightly doped drain region is approximately equivalent to a width of the source region and the drain region of the transistor or narrower than the width of the source region and the drain region of the transistor.
8. The solid-state imaging device according to claim 1 , wherein the lightly doped drain region does not exist outside of the gate electrode of the transistor in the width direction.
9. The solid-state imaging device according to claim 8 , wherein the width of the gate electrode refers to the length of the gate electrode in the width direction of the current path of the transistor.
10. The solid-state imaging device according to claim 1 , wherein the lightly doped drain region is narrower near the surface of the semiconductor substrate than a distance from the semiconductor surface.