Modified local segmented self-boosting of memory cell channels
A method of programming a memory system by selectively applying a program voltage to a selected wordline connected to a memory transistor to be programmed. A first bias voltage is applied to a first wordline adjacent to the source side of the selected wordline. The first bias voltage is also applied to a second wordline adjacent to the drain side of the selected wordline. A second bias voltage is applied to a third wordline adjacent to the drain side of the second wordline. A third bias voltage is applied to a fourth wordline adjacent to the source side of the first wordline. A pass voltage is also applied to the remaining wordlines that do not have one of a bias voltage and a program voltage applied, the pass voltage a selected voltage level.
1. A method of programming a memory system, the method comprising:
selectively applying a program voltage to a selected wordline connected to a memory transistor to be programmed;
applying a first bias voltage to a first wordline adjacent to a source side of the selected wordline;
applying the first bias voltage to a second wordline adjacent to a drain side of the selected wordline;
applying a second bias voltage to a third wordline adjacent to a drain side of the second wordline;
applying a third bias voltage to a fourth wordline adjacent to a source side of the first wordline, wherein the third bias voltage is different than the second bias voltage; and
selectively applying a pass voltage to remaining wordlines that do not have one of the first bias voltage, the second bias voltage, the third bias voltage, or the program voltage applied, the pass voltage being at a selected voltage level.
2. The method according to claim 1 , wherein the third bias voltage is set to ground.
3. The method according to claim 1 , wherein the first bias voltage is approximately 0-2 volts and the second bias voltage is approximately 2-3 volts.
4. The method according to claim 1 , wherein the program voltage is approximately 18 volts.
5. The method according to claim 1 , wherein one of the third wordline and the fourth wordline is a dummy wordline.
6. An apparatus for programming a memory system, the apparatus comprising:
a memory device coupled to receive a program signal, wherein the memory device, in response to the program signal, is configured to perform the following:
selectively apply a program voltage to a selected wordline connected to a memory transistor to be programmed;
apply a first bias voltage to at least one first wordline adjacent to a source side of the selected wordline;
apply the first bias voltage to at least one second wordline adjacent to a drain side of the selected wordline;
apply a second bias voltage to a third wordline adjacent to a drain side of the at least one second wordline;
apply a third bias voltage to a fourth wordline adjacent to the source side of the at least one first wordline, wherein the third bias voltage is different than the second bias voltage; and
selectively apply a pass voltage to remaining wordlines that do not have one of the first bias voltage, the second bias voltage, the third bias voltage, and or the program voltage applied, the pass voltage being at a selected voltage level.
7. The apparatus according to claim 6 , wherein the at least one first wordline comprises a single first wordline.
8. The apparatus according to claim 6 , wherein the at least one first wordline comprises two or more first wordlines.
9. The apparatus according to claim 6 , wherein the at least one second wordline comprises a single second wordline.
10. The apparatus according to claim 6 , wherein the at least one second wordline comprises two or more second wordlines.
11. The apparatus according to claim 6 , wherein the third bias voltage is set to ground.
12. The apparatus according to claim 6 , wherein the first bias voltage is approximately 0-2 volts and the second bias voltage is approximately 2-3 volts.
13. The apparatus according to claim 6 , wherein the program voltage is approximately 18 volts.
14. The apparatus according to claim 6 , wherein one of the third wordline and the fourth wordline is a dummy wordline.
15. A memory system comprising:
a plurality of strings of memory transistors arranged in parallel to form an array with a plurality of wordlines; and
a circuit coupled to the plurality of strings of memory transistors, the circuit to:
selectively apply a program voltage to a selected wordline connected to a memory transistor to be programmed;
selectively apply a first bias voltage to a first wordline adjacent to a source side of the selected wordline;
selectively apply the first bias voltage to a second wordline adjacent to a drain side of the selected wordline;
selectively apply a second bias voltage to a third wordline adjacent to a drain side of the second wordline;
selectively apply a third bias voltage to a fourth wordline adjacent to a source side of the first wordline, wherein the third bias voltage is different than the second bias voltage; and
selectively apply a pass voltage to remaining wordlines that do not have one of the first bias voltage, the second bias voltage, the third bias voltage, or the program voltage applied, the pass voltage being at a selected voltage level.
16. The memory system according to claim 15 , wherein the third bias voltage is set to ground.
17. The memory system according to claim 15 , wherein the first bias voltage is approximately 0-2 volts and the second bias voltage is approximately 2-3 volts.
18. The memory system according to claim 15 , wherein the program voltage is approximately 18 volts.
19. The memory system according to claim 15 , wherein one of the third wordline and the fourth wordline is a dummy wordline.